MIPI M-PHY

The M-PHY implements MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of a group of communication protocols defined by MIPI® Alliance standards intended for mobile system chip to chip communications. The M-PHY specification is specifically designed to be suitable for multiple protocols and for a wide range of applications.

The M-PHY includes transmitters and receivers to implement full-duplex operations. The IP supports multiple BURST modes, including HS and LS for improved power efficiency and multiple power saving modes where power consumption can be traded-off for recovery time.

The I/O and ESD are also built-in, providing a convenient, drop-in PHY. The design is optimized for high speed applications with robust timing and small silicon area.

• Compliant with MIPI Alliance MIPI M-PHY V4.1 Specifications
• Supports the standard RMMI interface compliant to M-PHY Specification
• Supports HS Mode (GEAR1~4, A/B)
• Supports data rates up to 11.6608Gbps per lane
• Supports M-PHY Type-I, Type-II
• Supports reference clock frequencies: 19.2/26/38.4/52MHz
• Supports LS-BURST, HS-BURST, STALL, SLEEP, HIBERN8 states
• Dynamic configuration and control via core ports
• Supports 10-/20-/40-bit width symbol bus
• Supports PRBS9/CUSTOM/CRPAT/CJTPAT pattern in test mode
• Supports Near-end BIST and Far-end loopback
• Supports CSI-3SM, LLI and SSIC IP
• Supports slew-rate control for reducing EMI

• Low power consumption
• Fully customizable
• High speed hub using VLPI low latency
• Small area
• Simple integration process
• Available options include
  • Test chips and test boards
  • FPGA integration support
  • Chip level integration

• Databook and physical implementation guides Netlist (Spice format for LVS)
• Library Exchange Format (LEF)
• Verilog Models
• GDSII to Foundry IP Merge
• Module integration guidelines
• Silicon validation report (when available)
• Evaluation board (when available)