MIPI C/D-PHY CSI/DSI TX and RX

The MIPI C/D-PHY + DSI/CSI Controller IP is a versatile solution designed for high-speed data transmission in mobile and multimedia applications. It integrates C-PHY and D-PHY in a single IP core, supporting both MIPI C-PHY 1.1 and D-PHY 2.0 standards. The IP features a compact design with built-in I/O and ESD protection, optimized for robust performance and low power consumption. It enables seamless connectivity with C-PHY and D-PHY based sensors, making it ideal for SoCs in consumer electronics, automotive, and IoT devices.

The Innosilicon C/D Combo PHY supports high-speed and low-speed modes for bidirectional data transfer. It offers both receiver and transceiver solutions, ensuring efficient data transmission in both C-PHY and D-PHY modes. The PHY is designed to coexist on the same IC pins, enabling dual-mode operation with minimal overhead.

The DSI Controller implements the MIPI DSI-2 protocol, enabling high-speed display communication. It packs and distributes pixel data to the C/D-PHY, supporting features like pixel/byte packing, low-level protocol, and lane management. The DSI TX transmits data to display, while the DSI RX reconstructs data streams from display, ensuring error-free communication. This IP is ideal for mobile devices, AR/VR headsets, and automotive displays, offering high performance and low latency.

The CSI Controller implements the MIPI CSI-2 protocol, facilitating camera-to-processor communication. It packs pixel data for transmission via the C/D-PHY and reconstructs data streams at the receiver end. The CSI TX/RX supports error detection (ECC/CRC) and lane management, ensuring reliable data transfer. This IP is widely used in smartphones, drones, surveillance cameras, and automotive ADAS systems, providing high-speed, low-power connectivity for image sensors.

• Compliant with MIPI Alliance Specification for D-PHY V2.0
• Compliant with MIPI Alliance Specification for C-PHY V1.1
• Compliant with MIPI Alliance Specification for DSI-2 V1.0
• Compliant with MIPI Alliance Specification for CSI-2 V2.0
• HS, LP, ULPS modes supported
• 4.5Gbps maximum data transfer rate per lane in D-PHY mode
• 3.5Gsps maximum data transfer rate per trio in C-PHY mode
• Asynchronous transfer in low power mode with a bit rate of 10Mbps in both C-PHY and D-PHY
• Unidirectional and bi-directional modes supported
• Skew-calibration for D-PHY supported
• ECC and CRC insertion supported
• Automatic termination control for HS and LP modes
• Buffers with tunable on-die-termination and advanced equalization
• Supports BIST logic
• Supports combo LVDS/TTL IP
• Supports combined with DSC1.2A for delivery

• Low power consumption
• Fully customizable
• High speed hub use VLPI low latency
• Small area
• Simple integration process
• Available options include
  • Test chips and test boards
  • FPGA integration support
  • Chip level integration

• Databook and physical implementation guides Netlist (Spice format for LVS)
• Library Exchange Format (LEF)
• Verilog Models
• GDSII to Foundry IP Merge
• Module integration guidelines
• Silicon validation report (when available)
• Evaluation board (when available)