Vendor: Synopsys, Inc. Category: Random Number Generator

True Random Number Generator for NIST SP 800-90c

The security strength of many systems and applications is dependent on the quality of random number generators.

Overview

The security strength of many systems and applications is dependent on the quality of random number generators. Many cryptographic operations require a source of random numbers, such as the creation of cipher keys and initial values for counters and protocol parameters.
The Synopsys True Random Number Generator (TRNG) Core for NIST SP 800-90c is compliant with NIST SP 800-90A/B/c and BSI AIS 20/31 specifications. It generates random numbers that are statistically equivalent to a uniformly distributed data stream. The core includes a NIST SP 800-90B approved conditioning circuit with a compliant noise source and NIST SP 800-90A approved Deterministic Random Bit Generator (DRBG) using the terminology preferred by the National Institute of Standards and Technology (NIST). The noise source does not depend on process-specific circuitry
and is therefore very portable across different ASIC and FPGA fabrication technologies. When implemented in silicon, the SynopsysTRNG can meet or exceed the highest commercial and US government SBU standards.

Benefits

  • NIST “Live, Enhanced NRBG”
  • Compliant with NIST SP 800-90A/B/c, AIS 20/31, FIPS 140-2 and FIPS 140-3
  • Designed for compliance with OSCCA certification
  • Customer configurable
  • Area: 60+ K ASIC gates
  • Performance: up to 3.2 Gbps at 500 MHz
  • Wide system clock dynamic range
  • Virtualization support (up to 8 TRNGs)
  • Selectable number of seed generators: 6 or 8
  • Background raw noise collection for fast reseeding
  • Redundant internal seed generators
  • Continuous statistical and on demand known answer health tests
  • Serial output stream for auxiliary uses: Differential power analysis; Timing analysis
  • Interfaces: Memory mapped (AXI/AHB/APB); Serial random bit streams (up to 3); Nonce interface compatible with DesignWare HDCP Content Protection ESMs

Applications

  • Security protocols
  • Networking
  • Mobile
  • Consumer electronics
  • IoT
  • Automotive
  • Government/military

What’s Included?

  • Verilog HDL developed in compliance with the IEEE 1364 Verilog-2005 standard
  • Testbench and test vectors
  • Sample synthesis script and constraints
  • Sample simulation script
  • Documentation
  • Reference software development kit (SDK)

Specifications

Identity

Part Number
dwc_true_random_number_generator_nist_sp800_90c
Vendor
Synopsys, Inc.
Type
Silicon IP

Security

RNG Type
TRNG

Files

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about Random Number Generator IP cores

What is True Random Number Generator for NIST SP 800-90c?

True Random Number Generator for NIST SP 800-90c is a Random Number Generator IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Random Number Generator?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Random Number Generator IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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