GLOBALFOUNDRIES 0.11um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
GLOBALFOUNDRIES 0.13um 1.2v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
Programmable 6-bit CMOS frequency divider
The programmable 6-bit CMOS frequency divider is a set of two independent circuits.
This IP is a programmable Analog PLL suitable for low frequency reference clock and large feedback clock divider.
This IP is a programmable Analog PLL suitable for high speed clock generation.
Phase-locked loop frequency synthesizer
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multip…
800/1000 MHz DLL-based frequency multiplier
090TSMC_MDLL_01 is a clock multiplier accept an input clock and generates a phase-locked output clock at a multiple of the input …
DVB-S demodulator / DSNG demodulator
The CMS0048 DVB-S/DSNG Demodulator is a high-performance (A)PSK demodulator core intended for DVB-S and DVB DSNG forward link app…
The CMS0059 Satellite Demodulator is a high-performance (A)PSK demodulator core intended for DVB-S, DVB-DSNG, DVB-S2 and DVB S2X …
Reference frequency oscillator
Reference oscillator is used to generate reference frequency and can work at the 1st or the 3rd harmonic of quartz resonator.
Tunable oscillator of reference frequency
Reference oscillator is used to generate reference frequency and can work at the 1st or the 3rd harmonic of quartz resonator.
5-bit programmable CMOS low-frequency divider
The 5-bit programmable CMOS low-frequency divider consists of an asynchronous pulse counter, a control logic and a multiplexer th…
0.32 to 10 MHz Phase-frequency detector
180TSMC_PFD_02 is a phase-frequency detector (PFD) forms a control signal for VCO tuning.
Programmable CMOS frequency divider (56..16383 dividing ratio)
The cell is 14-bit programmable frequency divider.
Programmable frequency divider (56 to 16383 dividing ratio)
The cell is 14-bit programmable frequency divider.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
24.84 MHz Phase-frequency detector with charge pump
180TSMC_PFD_01 is a phase-frequency detector (PFD) forms a control signal for VCO tuning.