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Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
PLL
SMIC 0.18um 1.8v APLL
This IP is a programmable Analog PLL suitable for low frequency reference clock and large feedback clock divider.
Overview
This IP is a programmable Analog PLL suitable for low frequency reference clock and large feedback clock divider. It contains a 1-32 input clock divider, a 1024-4578 feedback clock divider and a 1-8 output clock divider. By setting DM[4:0], DN[12:0] and DP[2:0] to different values according to different REFIN, CLK1 and CLKP will be locked at the multiples of input frequency.
Key features
- Process: SMIC 0.18um 1P6M CMOS logic process
- Supply voltage: 1.8v±10%
- Input reference clock frequency range: 30KHZ ~ 3MHZ
- Output clock CLK1 frequency range: 70MHZ ~ 150MHZ
- On chip filter capacitances
- Current: <3mA
- Operating junction temperature: - 40°C ~ +25°C ~ +125°C
- Two output clocks:
- CLKP: standard output from the output divider
- CLK1: output from VCO directly
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 180nm | G | Pre-Silicon |
Specifications
Identity
Part Number
SMIC18_PLL_15
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Provider
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Frequently asked questions about PLL IP cores
What is SMIC 0.18um 1.8v APLL?
SMIC 0.18um 1.8v APLL is a PLL IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic Pre-Silicon.
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.