Vendor: NTLab Category: Clock Generator

Programmable 6-bit CMOS frequency divider

The programmable 6-bit CMOS frequency divider is a set of two independent circuits.

Overview

The programmable 6-bit CMOS frequency divider is a set of two independent circuits. One of them is designed using 6-bit counter and is able to change input frequency dividing ratio with step 1. The second part is based on a set of serially connected dividers with the varied dividing ratio 2/3 and is able to change dividing ratio with step 0.5. Since this structure consists of the static triggers, current consumption is closed to zero when there is no input clock. The dividing ratio is 1…63. Input frequency is 10...300 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.

Key features

  • iHP SGB25V
  • Range of dividing ratio 1…63
  • Dividing ratio change with step 0.5
  • Compact structure
  • Portable to other technologies (upon request)

Block Diagram

Applications

  • PLL frequency synthesizer

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Specifications

Identity

Part Number
250iHP_FDIV_01
Vendor
NTLab
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Lithuania

Frequently asked questions about Clock Generator IP cores

What is Programmable 6-bit CMOS frequency divider?

Programmable 6-bit CMOS frequency divider is a Clock Generator IP core from NTLab listed on Semi IP Hub.

How should engineers evaluate this Clock Generator?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Clock Generator IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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