What is Programmable frequency divider (56 to 16383 dividing ratio)?
Programmable frequency divider (56 to 16383 dividing ratio) is a Clock Generator IP core from NTLab listed on Semi IP Hub.
Vendor:
NTLab
Category:
Clock Generator
Programmable frequency divider (56 to 16383 dividing ratio)
The cell is 14-bit programmable frequency divider.
Overview
The cell is 14-bit programmable frequency divider. It consists of ECL prescaler with variable dividing ratio 8/9 controlled by 3-bit swallow counter and CMOS 11-bit counter. The dividing ratio is 56…16383 and current consumption weakly depends on operating frequency (50..1050 MHz).
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Key features
- HP SGB25V
- Programmable dividing ratio (56 to 16383)
- Wide frequency range (50 to 1050 MHz)
- Small area
- Portable to other technologies (upon request)
Block Diagram
250iHP_NDIV_04 block diagram
Applications
- PLL frequency synthesizercy synthesizer
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Specifications
Identity
Part Number
250iHP_NDIV_04
Vendor
NTLab
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Lithuania
Frequently asked questions about Clock Generator IP cores
How should engineers evaluate this Clock Generator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Clock Generator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.