0.32 to 10 MHz Phase-frequency detector
180TSMC_PFD_02 is a phase-frequency detector (PFD) forms a control signal for VCO tuning.
Overview
180TSMC_PFD_02 is a phase-frequency detector (PFD) forms a control signal for VCO tuning. PFD compares phases of a divided VCO signal and a divided reference oscillator signal and detects phase difference. Charge pump (CP) generates pulses for the loop filter. The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscillator signal with required value. LD_MP<1:0> and LD_ACR outputs set the lock monitoring period and the lock detector accuracy, respectively.
Key features
- TSMC BiCMOS SiGe 180 nm
- Input signals with low amplitude
- Low disbalance of output current
- VCO divided signal buffering and optimization
- High accuracy
- Reference frequency from 0.32 MHz to 10 MHz
- Portable to other technologies (upon request)
Block Diagram
Applications
- Phase-locked loop synthesizer
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | BCDG2 | Silicon Proven |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about PLL IP cores
What is 0.32 to 10 MHz Phase-frequency detector?
0.32 to 10 MHz Phase-frequency detector is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.