What is 5-bit programmable CMOS low-frequency divider?
5-bit programmable CMOS low-frequency divider is a Clock Generator IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
NTLab
Category:
Clock Generator
5-bit programmable CMOS low-frequency divider
The 5-bit programmable CMOS low-frequency divider consists of an asynchronous pulse counter, a control logic and a multiplexer th…
Overview
The 5-bit programmable CMOS low-frequency divider consists of an asynchronous pulse counter, a control logic and a multiplexer that is able to commutate an input signal to output. The block is fabricated on TCMS BiCMOS 0.18 um technology.
Key features
- TCMS BiCMOS 0.18 um
- Continued range of dividing ratio (1…31)
- Low current consumption
- Compact structure
- Portable to other technologies (upon request)
Block Diagram
180TSMC_RDIV_01 block diagram
Applications
- PLL frequency synthesizer
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | BCDG2 | Silicon Proven |
Specifications
Identity
Part Number
180TSMC_RDIV_01
Vendor
NTLab
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Lithuania
Frequently asked questions about Clock Generator IP cores
How should engineers evaluate this Clock Generator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Clock Generator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.