PLL IP Listing

The CC-202IP Cell, can be cascaded to form a multistage RF amplifier/LNA/Filter.

• Amplifier
• Silicon Proven
• 44197

The CC-201IP block is a revolutionary, almost zero phase noise, clock gain IP block that possesses approximately 30 dB of signal …

• Voltage Reference
• Silicon Proven
• 44197

Silicon Library (SLI) HDMI 2.0 RX IP solution, which consists of PHY analog IP and digital LINK IP, is compliant with HDMI 2.0b standard.

• PHY
• HDMI
• TSMC
• 40nm
• G
• Available on request

Silicon Library (SLI) HDMI 2.0 TX IP solution, which consists of analog PHY IP and digital LINK IP, is compliant with HDMI 2.0b standard.

• PHY
• HDMI
• TSMC
• 12nm
• FFC
• Available on request

Ultra-low jitter, high SFDR LC-based PLL-12.5GHz for SerDes

• 5000 MHz
• 5 GBbps
• 10000 ns
• 25 mW
• 25 mW
• Compliant

This PLL is implemented in Global Foundries 22FDX CMOS technology.

• GlobalFoundries
• 22nm
• FDX
• Available on request

VBO Receiver with four and eight lanes for video communication

• PHY

A UCIe solution ready to support any protocol layer The D2D Adapter for UCIe combined with the UCIe PHY from a UCIe solution read…

• UCIe

qDSA-SW1.01 is a PDM-PCM converter to interface with a digital microphone.

• PLL

The ODT-LVDS-BID1G-12nm is a high-speed Bidirectional LVDS IO cell capable of operating up to 1 Gb/s.

• High-Speed
• In development

The ODT-CRX-2P5G-16FFCT is a high-speed clock receiver circuit capable of operating up to 2.5 GHz with low output jitter.

• Clock Generator

180XFAB_PLL_01 uses 2.25792GHz/2.4576GHz Phase locked loop frequency synthesizer for clock generation.

• Oscillator
• silicon proven
• Now

IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.

• TSMC
• 5nm
• N5FF

The USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specific…

• USB 2.0

The ONFI 3.2 compliant NAND Flash Controller IP Core is a full featured, easy to use, a synthesizable design that is easily integ…

• Controller

The QDR II SRAM Controller Intel FPGA IP provides an easy-to-use interface to QDR II SRAM and QDR II+ SRAM modules.

• Controller

The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry…

• Controller + PHY
• DDR2

The DDR and DDR2 SDRAM controllers handle the complex aspects of using DDR and DDR2 SDRAM—initializing the memory devices, managi…

• Controller
• DDR2

ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in energy efficient Systems on Chip.

• GlobalFoundries
• 22nm
• FDX

With sophisticated architecture and technology, the Vendor provides LPDDR5 IP solution with high performance and low power.

• Controller
• LPDDR5