Overview
The CC-201IP block is a revolutionary, almost zero phase noise, clock gain IP block that possesses approximately 30 dB of signal gain while contributing only 1.3nV per root Hz (rms) of circuit phase noise. The proprietary and patented design possesses a 2nd order bandpass function and is tunable from 100Mhz to 2.5Ghz. Since the IP block converts small signal, single ended inputs generated by clean clock sources, such as external fundamental and odd order crystals and sources, to amplified, differential, almost zero noise signals, the block is perfect for ADC/Track and Hold Clock Generation, DAC Clock Generation, Switched Capacitor Clock Generation and Distribution, can be used for PLL output filtering to reduce wideband harmonics and spurious frequencies, or simply used as a revolutionary ultra-low noise, high gain, Low Noise Amplifier.
Learn more about Voltage Reference IP core
This white paper will discuss the design challenges that IC designers are facing when developing the new GDDR 7 high-performance memory interface and highlight some of the possible solutions to overcome these challenges, ensuring compliance and robustness of the GDDR7 memory interface.
The design of modern Application Specific Integrated Circuits (ASICs) and Systems on a Chip (SoCs) in advanced process nodes can be differentiated by the on-die integration of analog functions, such as power management. Vidatronic offers this white paper to give some historical background on this trend and delve specifically into the integration of power management. Vidatronic IP solutions and the benefits they bring to ASIC and SoC designers are discussed.
Based on the system specification of a typical smart meter, this article demonstrates the importance of carefully selecting the power metering IP solution so that its specification matches the standard requirements and copes with the application challenges. This article then pinpoints thoroughly the various issues that must be taken into account for the selection of the Silicon IP and helps identify the possible trade-offs between the performance of the Mixed-signal Front-end (MFE) and that of the Power and energy Computation Engine (PCE).
System integrators often encounter problems on application boards too late in the design cycle, when bringing together Virtual Components (ViCs of silicon IPs) into a system. Some ViC performances may be degraded at higher levels (SoC and PCB), and thus the final system does not perform as well as expected. In other words, assembling high-performance ViCs together does not guarantee high-performance SoCs or systems when fundamental integration aspects are not addressed or key issues are violated during the integration process.
Today’s energy metering standards demand higher accuracy and lower power consumption which, in turn, challenges system designers to deliver more competitive AFEs. This article reviews those challenges and presents a solution based on a multiplexed channel architecture that delivers ultra-high resolution, along with very low-power consumption and silicon area.
Presented in this paper is a tool that automatically migrates analog designs from one process to another while keeping circuit and layout topologies.
