MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Rx IP Core in 28HPC+ aligns precisely with the D-PHY specification version 1.2, facilitating support for the Displ…
- MIPI D-PHY
- TSMC
- 28nm
- HPC+
- In Production
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Rx IP Core in 28HPC+ aligns precisely with the D-PHY specification version 1.2, facilitating support for the Displ…
MIPI D-PHY Tx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Tx IP Core fully complies with version 1.2 of the D-PHY specification.
HFT: Packet Filter for NSE's Tick to Trade Protocol for FPGA
In High Frequency trading, Any time spent in examining unwanted packets results in loss of Trading Advantage.
The logiMEM DDR3 SDRAM Memory Controller is a size optimized, flexible, parametric and synthesizable Synchronous DRAM Controller …
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devic…
eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP
eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption.
Linear Low-Dropout Regulator (Output Voltage 0.6V)
1-VIA’s VSCOM4L400ALDO0V6 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulatio…
Linear Low-Dropout Regulator (Output Voltage 0.9V)
1-VIA’s VSCOM4L400ALDO0V9 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulatio…
10M/100M/1G/10G Managed/Unmanaged (TSN) Ethernet Switch IP Core
Multi-port, multi-rate managed Ethernet switch with Time-Sensitive Networking (TSN) capabilities
4.4 GHz To 7.75 GHz Low phase Noise Fractional-N Synthesizer
The WEA48S55T is a broadband fractional–N frequency synthesizer with integrated phase sync function.
MMWave 80GHz PLL with VCO frequency range 19.00-20.25 GHz
MMWave 80GHz Analog FracN PLL with VCO frequency range 19.00-20.25 GHz, Including Integrated PFD, CP, LPF, VCO
Bandgap Voltage Reference (0.6V and 0.8V References)
1-VIA’s VSCOM4l400ABG IP is a 1.8V low-noise unbuffered programmable 0.6 and 0.8V Bandgap Voltage References (BGR) with eight 50u…
The Ceva-PentaG2 is a IP platform for implementing a wide range of user-equipment and IoT cellular modems.
CYB-RS-en core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
CYB-RS-de core implements the Reed Solomon decoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification.
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
SHA256 is a Secure Hash Algorithms which is one of the latest hash functions standarized by the U.S Federal Government.
Voltage/Current References - 1.21V ±0.5%, 600nA ±10% - GlobalFoundries 0.13µm Lite
This macro-cell is a low power voltage-current reference (1.21V / 600nA) with high accuracy (±0.5% over PVT) after trimming.
Scalable Edge NPU IP for Generative AI
Ceva-NeuPro-M is a scalable NPU architecture, ideal for transformers, Vision Transformers (ViT), and generative AI applications, …