10BASE-T1S Verification IP

The 10BASE-T1S Verification IP is compliant with IEEE 802.3 Specification and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a 10BASE-T1S interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment.10BASE-T1S verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.

10BASE-T1S Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

10BASE-T1S Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports 10BASE-T1S as per specification IEEE 802.3cg-2019
  • Supports MII
  • Supports Self-synchronizing Scrambler/Descrambler
  • Supports 4b/5b Encoding/Decoding
  • Supports DME(Differential Manchester Encoding)
  • Supports full duplex and half duplex operation
  • Supports clause 98 auto-negotiation
  • Supports PLCA (Physical layer Collision Avoidance)
• Supports MDIO slave and master model as per Clause 22 and Clause 45
• Supports G.999.1 Interface
• 10BASE-T1S Verification IP comes with complete UNH Test suite
• Supports the Upper layer protocols
• Supports IP in IP
• Supports Q in Q
• Full support for IEEE 802.1AZ (Energy Efficient Ethernet)
• Full support for IEEE 1588-2002,IEEE 1588-2008 and IEEE 1588-2019
• Supports Pause frame generation and detection
• Supports all types of TX and RX errors insertion/detection at each layer.
  • Under and oversize frame.
  • CRC errors
  • Framing errors
  • Pause frame errors
  • Disparity and Auto-negotiation errors
  • Invalid symbol insertion
  • Invalid AN sequence error insertion
• Comes with Tx BFM, Rx BFM, and Monitor
• Monitor supports detection of all protocol violations
• Built in coverage analysis
• Callbacks in master and slave for various events
• Status counters for various events in bus

• Faster testbench development and more complete verification of 10BASE-T1S designs.
• Easy to use command interface simplifies testbench control and configuration of 10BASE-T1S TX and RX.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the testcases.
• Examples showing how to connect various components, and usage of TX,RX BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.