Vendor: SmartDV Category: UFS Controller

UFS Synthesizable Transactor

UFS Synthesizable Transactor is compliant with JESD220B UFS specification and verifies UFS devices.

Overview

UFS Synthesizable Transactor is compliant with JESD220B UFS specification and verifies UFS devices. UFS is build on top of it to make it robust. UFS Synthesizable Transactor provides a smart way to verify the UFS component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's UFS Synthesizable Transactor is fully compliant with standard JESD220B UFS specification and provides the following features.

Key features

  • Full UFS Host and Device functionality
  • Supports UFS 2.1 draft specification
  • Supports high performance M-PHY type-1
  • Supports full UFS Host and Device functionality
  • Supports UFS driver layer over UniPro
  • Supports VIP interface at MPHY Serial, MPHY RMMI, Unipro CPort level
  • Supports UFS-Specified commands of Specification JESD220B
  • Supports Unified Memory Extension JESD220-1(Version 1.0)
  • Supports various UFS layers
    • UFS Command Set Layer (UCS)
    • UFS Transport Protocol Layer (UTP)
    • UFS Interconnect Layer (UIC)
  • Includes MIPI UniPro and M-PHY VIP for UFS Interconnect Layer verification
    • MIPI UniPro is adopted for data link layer
    • MIPI M-PHY is adopted for physical layer
    • 1 and 2 lane support
    • All PWM gears support
    • All HS gears support
    • All DME commands supported
    • Enter hibernate and exit hibernate supported
    • Complex LSS feature verification support to cover all cases, Like lane mapping, reverse lane mapping, errors in UPR sequences etc
    • Various types of error injection at Unipro and MPHY layers
    • L1.5 and Cport test mode features supported
    • Advanced L1.5, L2 and Cport error injection
    • All L2 Preemption and error cases supported
    • Supports Unipro 1.41 and Unipro 1.6 specs
    • Low power with multiple power operating modes
  • Supports boot mode operation
  • Supports device enumeration and discovery
  • Supports Multiple partitions (LUNs) with partition Management
  • Supports Multiple User Data Partition with Enhanced User Data Area options
  • Supports boot partitions and RPMB partition
  • Supports Reliable write operation
  • Supports Background operations
  • Supports Secure operations, Purge and Erase to enhance data security
  • Supports Write Protection options, including Permanent & Power-On Write Protection
  • Supports Signed access to a Replay Protected Memory Block
  • Supports HW Reset Signals
  • Supports Task management operations
  • Supports Power management operations
  • Supports automatic/user tag generation
  • Supports Error injection and detection in all levels of UFS protocol
  • Supports all types of error injection and detection
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

UFS Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the UFS testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Specifications

Identity

Part Number
UFS Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about UFS Controller IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about UFS Controller IP

What is UFS Synthesizable Transactor?

UFS Synthesizable Transactor is a UFS Controller IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this UFS Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UFS Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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