Vendor: SmartDV Category: V-By-One

VBYONE Synthesizable Transactor

VByOneHS Synthesizable Transactor provides an smart way to verify the VByOneHS component of a SOC or a ASIC in Emulator or FPGA p…

Overview

VByOneHS Synthesizable Transactor provides an smart way to verify the VByOneHS component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's VByOneHS Synthesizable Transactor is fully compliant with standard VByOne specification as 1.2/1.3/1.4/1.5 Specification and provides the following features.

Key features

  • Follows VByOne specification as 1.2/1.3/1.4/1.5
  • Support transmitter and Receiver Mode
  • Supports upto 32 serial lanes
  • Supports all byte lengths, color depths, and resolutions
  • Supports lane skew insertion in transmitter mode
  • Supports disparity and invalid code insertion in 8b/10b
  • Supports 10 bit, 20 bit, 40 bit parallel interface
  • Supports insertion of scrambler errors
  • Supports scrambler as in VByOneHS specification
  • Support on the fly generation of data
  • Supports detection and reporting the following errors
    • Invalid control character injection
    • Invalid data character injection
    • Invalid 10bit code injection
    • Sync errors
    • Scrambler errors
    • Disparity errors
    • Alignment errors

Block Diagram

V-By-One Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesiable transactors
  • Complete regression suite containing all the VByOneHS testcases
  • Examples showing how to connect various components, and usage of Synthesiable VIP
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Specifications

Identity

Part Number
V-By-One Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about V-By-One IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about V-by-One IP cores

What is VBYONE Synthesizable Transactor?

VBYONE Synthesizable Transactor is a V-By-One IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this V-By-One?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this V-By-One IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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