Vendor: SmartDV Category: Protocol Bridge

TileLink Synthesizable Transactor

TileLink Synthesizable Transactor provides a smart way to verify the TileLink component of a SOC or a ASIC in Emulator or FPGA pl…

Overview

TileLink Synthesizable Transactor provides a smart way to verify the TileLink component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's TileLink Synthesizable Transactor is fully compliant with standard TileLink Specification 1.8.1 and provides the following features

Key features

  • Compliant with TileLink specification Version 1.8.1.
  • Supports TileLink Master, TileLink Slave and TileLink Interconnect.
  • Supports TileLink Uncached Lightweight (TL-UL),TileLink Uncached Heavy weight (TL-UH) and TileLink Cached (TL-C) conformance levels.
  • Supports Cache-coherent shared memory.
  • Out-of-order completion support.
  • Burst fragmentation support.
  • Supports constrained randomization of protocol attributes.
  • Slave, Interconnect and Master support fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
  • Ability to inject errors during data transfer.
  • Ability to configure the width of all signals.
  • Programmable Timeout insertion.
  • Rich set of configuration parameters to control TileLink functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, timings and protocol violations.
  • Callbacks in Master, Slave and Interconnect for various events.
  • Status counters for various events on bus.
  • TileLink Synthesizable Transactor comes with complete testsuite to test every feature of TileLink specification.

Block Diagram

TileLink Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV VIP's.
  • All UVM sequences/testcases written with VIP can be reused.
  • Runs in every major emulators environment.
  • Runs in custom FPGA platforms.

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the TileLink testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
TileLink Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Protocol Bridge IP core

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As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about Protocol Bridge IP cores

What is TileLink Synthesizable Transactor?

TileLink Synthesizable Transactor is a Protocol Bridge IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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