Vendor: SmartDV Category: USB

USB PD Synthesizable Transactor

USB Power Delivery Synthesizable Transactor provides an smart way to verify the USB Power Delivery component of a SOC or a ASIC i…

Overview

USB Power Delivery Synthesizable Transactor provides an smart way to verify the USB Power Delivery component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's USB Power Delivery Synthesizable Transactor is fully compliant with standard USB Power Delivery Specification and provides the following features.

Key features

  • USB PD Features
    • Supports USB Power Delivery Specification 3.1,3.0, 2.0 and 1.0
    • Supports USB Type-C Cable and Connector Specification
    • Supports Cable plug communication
    • Supports all Resets: Hard, Soft and Cable Resets
    • Supports all types of packets
    • Supports BFSK and BMC signaling of physical layer
    • Supports BIST
    • Supports Cable plug communication
    • Supports Timer as per specification
    • Supports Counters as per specification
    • Supports data role swap and power role swap
    • Supports Structured and Unstructured VDM
    • Supports Device and System Policy
    • Supports injecting timing variations in physical layer
    • Supports Error Injection
    • CRC error
    • Message type errors
    • FIFO depth programmable
    • Auto response generation
    • Supports all Swappings: Power role, Data role, Fast power role and Vconn swap
    • Supports chunked transaction
    • Supports included extended power supply capabilities and status
    • Notifies the test bench of significant events such as transactions, warnings, and protocol violations
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
  • TYPE-C Features
    • Supports USB Type-C Cable and Connector Specification 3.0,2.0 and 1.0
    • Supports Debug accessory operation
    • Supports Audio accessory operation
    • Supports Plug Orientation/Cable Twist Detection
    • Supports all the connection fsm states

Block Diagram

USB PD Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the USB Power Delivery testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
USB PD Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about USB IP core

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SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about USB IP cores

What is USB PD Synthesizable Transactor?

USB PD Synthesizable Transactor is a USB IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this USB?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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