Vendor: SmartDV Category: Protocol Bridge

OpenCores Wishbone B3 Synthesizable Transactor

OpenCores Wishbone B3 Synthesizable IP provides a smart way to verify the OpenCores Wishbone B3 component of a SOC or a ASIC in E…

Overview

OpenCores Wishbone B3 Synthesizable IP provides a smart way to verify the OpenCores Wishbone B3 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's OpenCores Wishbone B3 Synthesizable IP is fully compliant with standard OpenCores Wishbone B3 Specification and provides the following features

Key features

  • Compliant to OpenCores Wishbone B3 Protocol
  • Support for all types of Wishbone devices
    • Master
    • Slave
  • Supports programmable wait states
  • Supports programmable Retry insertion
  • Supports programmable Error insertion
  • Supports configurable transfer size for read and write transactions
  • Supports linear,Fixed and Wrap burst sizes
  • Supports flexibility to send completely configured data
  • Ability to inject errors during data transfer
  • Supports on-the-fly protocol and data checking

Block Diagram

OpenCores Wishbone B3 Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the OpenCores Wishbone B3 testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
OpenCores Wishbone B3 Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Protocol Bridge IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about Protocol Bridge IP cores

What is OpenCores Wishbone B3 Synthesizable Transactor?

OpenCores Wishbone B3 Synthesizable Transactor is a Protocol Bridge IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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