Vendor: SmartDV Category: Spacewire

SpaceWire Synthesizable Transactor

SpaceWire Synthesizable Transactor provides a smart way to verify the SpaceWire component of a SOC or a ASIC in Emulator or FPGA …

Overview

SpaceWire Synthesizable Transactor provides a smart way to verify the SpaceWire component of a SOC or a ASIC in Emulator or FPGA platform. The SpaceWire Synthesizable Transactor is compliant with ECSS-E-ST-50-12C specification and verifies SpaceWire interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create most wide range of scenarios to verify the DUT effectively.

Key features

  • Supports ECSS E‐ST‐50‐12C Standard
  • Supports speeds between 2 Mb/s and 400 Mb/s
  • Supports Full SpaceWire Functionality
  • Supports Data-Strobe (DS) encoding
  • Support Encoding/Decoding Link interface
  • Support Flow control and link Initialization
  • Includes Time-Codes support
  • Supports all types of errors detected as given below:
    • Link errors
    • Disconnect error
    • Parity error
    • Escape sequence error
    • Character sequence error
    • Credit error
    • Empty packet error
    • Network errors
    • Link error
    • EEP received
    • Destination address error
  • Provides Link error recovery
  • Supports Exchange of silence error recovery procedure
  • Supports error injection capability for post silicon validation.
  • Fully synthesizable
  • Supports static synchronous design
  • Supports positive edge clocking and no internal tri-states

Block Diagram

SpaceWire Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the SpaceWire testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
SpaceWire Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Spacewire IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about SpaceWire IP cores

What is SpaceWire Synthesizable Transactor?

SpaceWire Synthesizable Transactor is a Spacewire IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Spacewire?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Spacewire IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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