Video Design Framework for Multi-camera Vision Applications
The logiREF-ACAP-VDF "ACAP IP Framework for Multi-Camera Vision Applications" enables Xylon logiVID-ACAP-6CAM ACAP Vision Develop…
The logiJPGD-LS Motion JPEG (MJPEG) Decoder is Xylon’s logicBRICKS IP core for still image and video decompression applications o…
The logJPGE-LS Motion JPEG (MJPEG) Lossless Encoder is a Xylon's logicBRICKS IP Core for still image and video compression applic…
HDR ISP framework for multi-camera applications
Xylon offers a logicBRICKS IP suite for implementing High-Dynamic Range (HDR) Image Signal Processing (ISP) pipelines in embedded…
The logiHSSL IP core enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and X…
The logiCLK is a programmable clock generator logicBRICKS IP core with twelve independent and fully configurable clock outputs.
The logiSDHC is the Secure Digital (SD) card Host Controller IP core from the Xylon logicBRICKS IP core library.
Bitmap 2.5D Graphics Accelerator
The logiBMP is 2.5D graphics accelerator from Xylon logicBRICKS IP library, optimized for Xilinx FPGAs and designed to speed up g…
Compact Multilayer Video Controller
The logiCVC-ML IP core is an display graphics controller that enables an easy video and graphics integration into embedded system…
The logiJPGE Motion JPEG Encoder is JPEG standard Baseline DCT compliant encoder IP core for still image and video decompression …
The logiSLVDS_RX IP core enables easy interfacing of ultra high resolution Sony CMOS image sensors to image signal processing pip…
High Dynamic Range (HDR) Pipeline
The logiHDR is an Ultra High Definition (UHD) HDR pipeline designed for digital processing and image quality enhancements of the …
The logiDROWSINE is a computer vision IP core that detects driver drowsiness and distraction based on facial movements monitored …
The logiJPGD Multi-Channel Motion JPEG Decoder is JPEG standard Baseline DCT compliant decoder IP core for still image and video …
UHD Image Signal Processing (ISP) Pipeline
The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital proc…
Color Camera Sensor Bayer Decoder
Today most common single-chip cameras use CMOS sensors with pixels arranged in Bayer color pattern.
The logiI2S IP core from Xylon's logicBRICKS™IP library is a module for I2S audio data receiving and/or transmitting.
Versatile Video Input - frame grabber
The logiWIN Versatile Video Controller is a picture process unit that accepts versatile video input streams, converts them to the…
Bit Block Transfer 2D video accelerator
The logiBITBLT is 2D graphic accelerator or BitBlitter IP core from Xylon logicBRICKS™ IP library.
ACAP HDR Image Signal Processing Framework
The ACAP HDR Image Signal Processing Framework is intended to showcase a logicBRICKS IP suite implementation of High-Dynamic Rang…