Vendor: Xylon Category: Video Processing

Motion JPEG Encoder

The logiJPGE Motion JPEG Encoder is JPEG standard Baseline DCT compliant encoder IP core for still image and video decompression …

Overview

The logiJPGE Motion JPEG Encoder is JPEG standard Baseline DCT compliant encoder IP core for still image and video decompression applications on Xilinx All Programmable SoC and FPGA devices. It includes all logic blocks necessary for quick implementations of AXI4 streaming based SoC architectures and enables on-the-fly JPEG compression of input video with resolutions up to 2048x2048.

The logiJPGE decreases the data throughput required for video transport, i.e. in the Ethernet-based video camera, the required bandwidth of 2400 Mbps for FullHD video can be decreased to easily managable 100 Mbps!

The logiJPGE is fully embedded into Xilinx Vivado Design Suite to hide a complexity from the end-user and to make its integration with the on-chip AMBA AXI4 bus easy. The logiJPGE reference design, which is on request available from Xylon, can be used as a starting point to evaluate and develop Xilinx-based MJPEG video processing embedded systems.

Key features

  • Supports Xilinx® Zynq®-7000 AP SoC and 7 series FPGA families
  • Compliant with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard
  • On-the-Fly video encoding to Motion JPEG stream
  • Configurable video compression factor
  • Video input/output resolutions up to 2048x2048
  • Pixel formats: YUV 4:2:0 and YUV 4:2:2
  • No programming required
  • AMBA® AXI4-Stream compliant video input/output
  • IP deliverables include documentation and technical support
  • Reference design available on request
  • Available for Xilinx Vivado® Design Suite

Block Diagram

Applications

  • camera designs
  • Multi-camera ADAS applications
  • Multi-camera Surveillance

What’s Included?

  • IP core in Vivado compatible format
  • documentation
  • tech support
  • ref. design on request

Specifications

Identity

Part Number
logiJPGE
Vendor
Xylon
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Croatia

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is Motion JPEG Encoder?

Motion JPEG Encoder is a Video Processing IP core from Xylon listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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