Overview
The logiCLK is a programmable clock generator logicBRICKS IP core with twelve independent and fully configurable clock outputs. While six clock outputs can be fixed by generic parameters prior to the implementation, the other six clock outputs can be either fixed by generics or dynamically reconfigured in a working device. The Dynamic Reconfiguration Port (DRP) interface gives system designers the ability to change the clock frequency and other clock parameters while the design is running by mean of a set of memory-mapped PLL configuration and status registers.
Xylon uses the logiCLK IP core in free and pre-verified Graphics Processing Unit (GPU) reference designs prepared for popular Zynq-7000 AP SoC based development kits, i.e. the logiREF-ZGPU-ZED design for the ZedBoard™ development kit from Avnet Electronics Marketing. This graphics engine reference design uses the logiCLK IP core as a programmable source of a video clock signal, which must be run-time changed to support different standard display (video) resolutions. Xylon’s software drivers (Linux, Microsoft Windows Embedded Compact) for graphic logicBRICKS IP cores include support for the logiCLK IP core. The drivers accept the input clock frequency and desired output frequencies as input parameters, and automatically program the logiCLK configuration bits.
Learn more about Clock Generator IP core
Using our “Specman agent approach for the Mixed Verification” along with exploiting “real” feature of Specman version 8.2, we can introduce directed/constrained randomization to the frequencies needed for the analog modules which are interacting with the DUT (Design Under Test). This approach gives complete controllability over the clock frequencies, which can be directly randomized and modified on-the-fly from the testcase, as the scenario may demand.
As clocks speed increase and the number of clocks increases, a programmable clock generator may offer a better system and EMI design solution
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