Overview
Xylon offers a complete logicBRICKS IP suite for implementing High-Dynamic Range (HDR) Image Signal Processing (ISP) pipelines in embedded designs based on Xilinx FPGA, SoC, MPSoC or ACAP programmable devices. HDR ISP pipelines enable crisp camera video under altering and rough lighting conditions in next-generation multi-channel embedded systems for use in automotive, surveillance, medical and similar video and vision AI applications.
logicBRICKS ISP IP cores enable parallel processing of multiple Ultra HD video inputs in different Xilinx devices, ranging from the small Xilinx Artix® FPGAs to the latest Xilinx Versal™ Adaptive Compute Acceleration Platform (ACAP) devices.
The logiREF-MULTICAM-ISP demonstrates these capabilities and shows how, in comparison to simple instantiation of multiple ISP pipelines within a single programmable device, Xylon’s logicBRICKS ISP pipeline allows for tremendous savings of up to 50 % of valuable programmable logic.
Learn more about ISP Image Signal Processor IP core
Intigia has developed AceleradorSNN, a third-generation artificial intelligence cognitive system. This architecture integrates a Neuromorphic Processing Unit (NPU) based on Spiking Neural Networks (SNNs) to process asynchronous data from Dynamic Vision Sensors (DVS), alongside a dynamically reconfigurable Cognitive Image Signal Processor (ISP) for RGB cameras.
Jiang Wang, Arm
Cadence's industry-first eUSB2V2 IP, built on the advanced TSMC N3P process and compliant with the latest embedded USB2 Version 2 standard, transforms computing devices by delivering unprecedented capabilities for laptops, AI video devices, and advanced image signal processor (ISP) systems.
When developing system-on-chip (SoC) solutions, the key features often minimize size, maximize performance, and achieve low power consumption while decreasing costs. These requirements are true for most industries, including AI-powered consumer devices, energy-intensive data centers, cloud-based enterprise systems, and smart autonomous vehicles.
Vinod Khera, Cadence
In this paper, we discuss the Transaction Level Model which is being developed to act as Virtual Prototype in digital image processors designed to fit into mobile applications. As part of our developments new methodology TLMdevice is also defined which provides way to connect TLM simulations to communicate with not only virtual host devices such as Graphical window, Keyboards but also real host devices like UART, Display and Sensors, so that data can be easily sent and received to/from during TLM simulation run
