How to simplify power design development and evaluation for FPGA-based systems
Validation of power supply voltage at the FPGA; real-time monitoring of Vccint power consumption; realistic power estimates using accurate on-die temperature measurement.
Vendor:
Xilinx, Inc.
Category:
Control Logic
LD-based Parallel Latch
The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width.
Overview
The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width. Options provided are Clock Enable; Asynchronous Set, Clear and Init; and Synchronous Set, Clear and Init. It can optionally generate output as a Relationally Placed Macro (RPM) or as unplaced logic. Output in RPM form is columnar.
Specifications
Identity
Part Number
LD-based Parallel Latch
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Control Logic Accelerator IP cores
What is LD-based Parallel Latch?
LD-based Parallel Latch is a Control Logic IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Control Logic?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Control Logic IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.