Vendor: Xilinx, Inc. Category: USB

XPS USB 2.0 Device

With this core, the Xilinx Universal Serial Bus 2.0 High Speed Device provides a control interface to internal registers via a 32…

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Overview

With this core, the Xilinx Universal Serial Bus 2.0 High Speed Device provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6.

This PLB slave interface supports single beat read and write data transfers (no burst transfers). This interface is suitable for USB-centric,high-performance designs, bridges and legacy port replacement operations.

Key features

  • Compliant with the USB 2.0 Specification
  • Supports High Speed and Full Speed.
  • Has a 32-bit OPB Slave Interface
  • Has a 32-bit OPB Slave Interface
  • Supports positive and negative ULPI clocks.
  • Has eight endpoints, including one control endpoint 0. Endpoints 1 - 7 may be bulk, interrupt, or isochronous. Endpoints are individually configurable.
  • Uses Block RAM for endpoint buffers. Each endpoint has two ping-pong buffers.

Specifications

Identity

Part Number
EF-DI-USB2-DEVICE-SITE
Vendor
Xilinx, Inc.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

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Frequently asked questions about USB IP cores

What is XPS USB 2.0 Device?

XPS USB 2.0 Device is a USB IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this USB?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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