Low-Power Design for Multi-Display and High Quality Image Processing
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VeriSilicon Microelectronics (Shanghai) Co., Ltd. (VeriSilicon, 688521.SH) is a leading public company that provides custom silicon solutions, leveraging its comprehensive and proprietary portfolio of semiconductor IPs.
VeriSilicon possesses six categories of in-house processing IPs, namely Graphics Processing Unit (GPU) IP, Neural Network Processing Unit (NPU) IP, Video Processing Unit (VPU) IP, Digital Signal Processing (DSP) IP, Image Signal Processing (ISP) IP, and Display Processing IP, as well as more than 1,700 analog and mixed-signal IPs, RF IPs, and interface IPs.
Leveraging its own IPs, VeriSilicon has developed a wealth of software and hardware custom chip design platforms targeting Artificial Intelligence (AI) applications, covering always-on ultralight spatial computing devices such as smartwatches and AI/AR glasses, high-efficiency edge computing devices such as AI PCs, AI phones, smart cars, and robots, as well as high-performance cloud computing devices like data centers and servers.
In response to the trend of System-on-Chip (SoC) evolving towards System-in-Package (SiP) driven by the demand for large computing power, VeriSilicon put forward the concepts of "IP as a Chiplet”, "Chiplet as a Platform", and "Platform as an Ecosystem”. The company keeps advancing the R&D and industrialization of its Chiplet technologies and projects from the perspective of interface IP, Chiplet architecture, advanced packaging technology, and others for AI-Generated Content (AIGC) and autonomous driving solutions.
Under its unique “Silicon Platform as a Service” (SiPaaS) business model, VeriSilicon serves a broad range of market segments, including consumer electronics, automotive electronics, computer and peripheral, industrial, data processing, Internet of Things (IoT), among others. Its main customers include fabless, IDM, system vendors (OEM/ODM), large internet companies, and cloud service providers.
Founded in 2001 and headquartered in Shanghai, China, VeriSilicon has 9 design and R&D centers, along with 11 sales and customer service offices worldwide. VeriSilicon currently has more than 2,000 employees.
Low-Power Design for Multi-Display and High Quality Image Processing
SEC 5nm LVH 6T Multi-Bits Latch
SEC 5nm LVH 6 track High Density Multi-Bits Latch
TSMC 12nm FFC 6track Delay Cells
TSMC 12nm FFC 6 track High Density Delay Cells
SMIC 0.13um 1.2V<->3.3V level shifter,1.2v/3.3v operating voltage
SMIC 0.13um 1.2V3.3V Level Shfiter Library
SMIC 0.13um Power Management Kit,1.2v operating voltage
SMIC 0.13um Power Management Kit Library
SMIC 0.13um 6 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.13um 6T HVT High-Density Standard Cell Library
High performance image signal processing for auto and industrial markets
Ultra-low power image signal processing for AIoT and wearable markets
Huali 28nm HKCP process Multiple Power Supply IO library
The Multiple I/O Library supports both 2.5V analog IO cells & 3.3V digital IO cells.
GLOBALFOUNDARIES 22nm FDSOI LVDS Transceiver Pad
The LVDS IO library provides IO cells for LVDS transmitter and receiver.
GLOBALFOUNDRIES 22nm High Density Single-Port SRAM Compiler
VeriSilicon GLOBALFOUNDRIES 22FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for GLOBALFOUNDRIES FDSOI 22nm proc…
GLOBALFOUNDRIES 22nm Low Leakage Single-Port SRAM Compiler
VeriSilicon GLOBALFOUNDRIES 22FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for GLOBALFOUNDRIES FDSOI 22nm proc…
GLOBALFOUNDRIES 22nm Low Power Single-Port SRAM Compiler
VeriSilicon GLOBALFOUNDRIES 22FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for GLOBALFOUNDRIES FDSOI 22nm proc…
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and…
SMIC 0.11um USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of 1-Clock and 4-Data lanes.
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock a…
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Slave V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Master V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.