VeriSilicon Introduces GLTiny™ 3D GPU Programming Model for Ultra-Low-Power, Memory-Efficient Wearable Devices
Optimized GLTiny Model Brings Rich 3D Graphics to Resource-Constrained Wearable Devices Powered by OpenGL ES GPUs
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
MIPI PHY
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Slave V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
Overview
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. It can support Slave side. Each lane supports 2.5Gbps in High-Speed mode and 10Mbps/lane in Low-Power escape mode. The target applications are CSI-2 and DSI physical layers.
Key features
- Process: GLOBALFOUNDARIES 22nm FDSOI 0.8V/1.8V
- 80 to 2500 Mbps data rate per lane in DPHY HS mode
- 80 to 2500 Msps symbol rate per lane in CPHY HS mode
- All lanes support HS and ULPS modes in forward direction
- All lanes support Escape (LPDT, Trigger) mode in forward direction
- D0 lane support reverse Escape mode (LPDT, Trigger) and Turn-Around
- Three 3phase encoded data lanes for CPHY Mode (T0 lane is bi-dir)
- Support one clock and four data lanes for DPHY Mode (D0 lane is bi-dir)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 22nm | FDX | In Production |
Specifications
Identity
Part Number
GF22FDSOIV18_DPHYRX_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Standards & Interfaces
MIPI PHY
MIPI D-PHY
Provider
Learn more about MIPI PHY IP core
VeriSilicon Introduces CPP2000 Camera Post-Processing IP for Embodied Robotics and Mobile Vision Applications
VeriSilicon today announced its high-performance CPP2000 Camera Post-Processing (CPP) IP, expanding the company’s Image Signal Processing (ISP) solutions with advanced post-processing capabilities.
VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
VeriSilicon today announced that its VC9800D Video Processing Unit (VPU) IP supports AV2 decoding, further expanding the company’s advanced video codec portfolio for next-generation video and streaming applications.
Hexagon Semi’s HX77 AR Display Processor Achieves Ultra-Low Power Consumption with VeriSilicon’s Nano IP Portfolio
VeriSilicon’s Mature GPU, Display Processing, and DeWarp IPs Collaboratively Enable Highly Integrated, Low-Latency AR Display Processing
VeriSilicon Enhanced ISP8200-FS Series IP Achieves ASIL B Functional Safety Certification
These enhanced IPs have successfully achieved ISO 26262 ASIL B functional safety certifications issued by TÜV NORD, an international inspection and certification institution, further validating their suitability and reliability for ADAS and autonomous driving applications.
VeriSilicon’s NPU IP VIP9000NanoOi-FS has achieved ISO 26262 ASIL B certification
This IP features an architecture streamlined for seamless SoC integration, delivering high-quality inference with low power consumption and a compact silicon footprint. The certificate was issued by SGS-TÜV Saar, an international testing, inspection and certification institution.
Frequently asked questions about MIPI PHY IP
What is GLOBALFOUNDRIES 22nm FDX MIPI DPHY Slave V1.2?
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Slave V1.2 is a MIPI PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for globalfoundries In Production.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.