IP Accelerated (Bye Bye EDA 360)
Eric Esteve
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
MIPI PHY
HLMC 55nm EF MIPI DPHY V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.
Overview
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both Master and Slave side. Each lane supports 2.5Gbps in High-Speed mode and 10Mbps/lane in Low-Power escape mode. The target applications are CSI-2 and DSI physical layers.
Key features
- Process:HLMC 55nm EF/LP Process
- 80 to 2500 Mbps data rate per lane in DPHY HS mode
- All lanes support DPHY HS and ULPS modes in the forward direction
- All data lanes support Escape mode(LPDT, Trigger) in the forward direction
- D0 lane supports reverse Escape mode (LPDT, Trigger) and Turn-around
- Lane number: 1 clock + 4 data
- On-chip differential 100? terminations with calibration
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| Huali | 55nm | LP | Silicon Proven |
Specifications
Identity
Part Number
HLMC55LLV12_DPHY_02
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Standards & Interfaces
MIPI PHY
MIPI D-PHY
Provider
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Frequently asked questions about MIPI PHY IP
What is HLMC 55nm EF MIPI DPHY V1.2?
HLMC 55nm EF MIPI DPHY V1.2 is a MIPI PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for huali Silicon Proven.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.