Silicon Library Inc. IP Cores

This IP supports operational data rates 80Mbps to 1.5Gbps per One lane for HS mode, and up to 10Mbps for LP modes transfer rates.

• MIPI D-PHY
• GlobalFoundries
• 55nm
• LPe

This MIPI DPHY/LVDS Combo Tx PHY IP is designed to the MIPI D-PHY 1.2 specifications and LVDS specifications.

• GlobalFoundries
• 55nm
• LPe

SD4.x UHSII is PHY IP solution for UHS-II interface for next generation of ultra high speed used in both SDHC and SDXC.

• Single-Protocol PHY

eDP (Embedded Displayport) Transceiver Link/PCS IP core is compliant with eDP 1.4a/DP 1.3 specification.

• Displayport
• silicon-proven
• VESA eDP Specification ver.…

HDMI 1.4b compliant, 2.97 Gbps

• SMIC
• 55nm
• LL
• In Production

HDMI 1.4b compliant, 2.97 Gbps

• SMIC
• 40nm
• LL
• In Production

HDMI 1.4b compliant, 2.97 Gbps

• UMC
• 40nm
• LP
• In Production

HDMI 1.4b compliant, 2.97 Gbps

• SMIC
• 40nm
• LL
• In Production

This MIPI DPHY Tx PHY IP is designed to the MIPI D-PHY 1.2 specifications.

• MIPI D-PHY
• TSMC
• 130nm
• BCD+

eDP/DP_TX consists of electrical sub-blocks of main-link and AUX channel of PHY for eDP/DP TX.

• Single-Protocol PHY
• under development
• VESA eDP/DP Specification v…

EDP_RX consists of electrical sub-blocks of main-link and AUX channel of PHY for eDP RX.

• Single-Protocol PHY
• silicon-proven
• VESA eDP Specification ver.…

eDP (Embedded Displayport) receiver Link/PCS IP core is compliant with eDP 1.4a/DP 1.3 specification.

• Displayport
• silicon-proven
• VESA eDP Specification ver.…