Vendor: Silicon Library Inc. Category: Multi-Protocol PHY

MIPI D-PHY/LVDS Combo TX IP

Compliant with both MIPI D-PHY version 1.2 and LVDS specifications that can be applied to OpenLDI V0.95

PHY GlobalFoundries 55nm LPe View all specifications

Overview

Silicon Library (SLI)’s MIPI D-PHY/LVDS Combo Tx IP solution is compliant with both MIPI D-PHY version 1.2 and LVDS specifications that can be applied to OpenLDI V0.95, which is the best solution to save both the pin counts and die area of modern SoCs. This IP solution is provided as the combination of physical layer (PHY) hard macro and D-PHY Control and Interface Logic (CIL) soft macro. Each of six lanes, supporting a maximum data rate of 1.5 Gbps, can be configured as either data lane or clock lane according to the pin assignment preference. Two PLLs with programmable frequency dividers are included in PHY.

This IP is available as Silicon proven ‘off-the-shelf’ product in Global Foundries 55nm.

Key features

MIPI D-PHY Ver1.2 compliant Tx

  • Supports both HS mode (from 80Mbps to 1.5Gbps) and LP mode (up to 10Mbps)
  • Each lane can be configured as ether a data lane or a clock lane
  • Two PLLs with programmable frequency dividers
  • Supports PHY Protocol Interface (PPI)

LVDS compliant Tx

  • Supports from 80Mbps to 1.5Gbps data rates
  • Supports reduced swing mode
  • Applicable to OpenLDI V0.95
  • Supports Dual LVDS mode by using two sets of this IP solution

Testability

  • At Speed Test by Loopback BIST
  • PLL bypass mode
  • Analog test

Block Diagram

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Silicon Options

Foundry Node Process Maturity
GlobalFoundries 55nm LPe —

Specifications

Identity

Part Number
MIPI D-PHY/LVDS Combo TX IP
Vendor
Silicon Library Inc.
Type
Silicon IP
Controller / PHY
PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about Multi-Protocol PHY IP cores

What is MIPI D-PHY/LVDS Combo TX IP?

MIPI D-PHY/LVDS Combo TX IP is a Multi-Protocol PHY IP core from Silicon Library Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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