MIPI DPHY-Rx
Complete PHY solution that is fully compliant to MIPI D-PHY specification version 1.2
Overview
Silicon Library (SLI) MIPI® D-PHY RX IP is a complete PHY solution that is fully compliant to MIPI D-PHY specification version 1.2, enabling easy integration of MIPI® D-PHY interface into low-power modern SoCs. The solution consists of Analog PHY and digital Control and Interface Logic (CIL). PHY is provided as a hard macro while CIL is provided as a synthesizable soft macro. This IP solution can be applied to both MIPI® Camera Serial Interface (CSI-2) and MIPI® Display Serial Interface (DSI) protocols. Both High-Speed (HS) and Low-Power (LP) modes are supported with one clock lane and four data lanes.
This PHY IP is available as Silicon proven ‘off-the-shelf’ IP in major fabs and technology nodes of 22nm and 55nm.
Key features
- Compliant with MIPI® D-PHY specification version 1.2
- One clock lane and four data lanes
- PHY Protocol Interface (PPI)
- Supports synchronous data transfer in high speed (HS) mode, covering 80M-1.5Gbps
- Supports asynchronous data communication in low power (LP) mode at up to 10Mbps
- Configurable skew adjustment
- Supports Ultra-Low Power State
- Sequence error detection mechanism
Block Diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 130nm | BCD+ | — |
Specifications
Identity
Standards & Interfaces
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about MIPI PHY IP
What is MIPI DPHY-Rx?
MIPI DPHY-Rx is a MIPI PHY IP core from Silicon Library Inc. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.