MAXVY Technologies Pvt Ltd IP Cores

The Low Pin Count (LPC) interface is a low bandwidth bus with up to 33 MHz performance.

• Verification IP

The vendor provides configurable GDDR6 verification IP.

• Verification IP
• Controller

The TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus.

• Temperature Sensor

The vendor provides configurable CPRI TX/RX verification IP.

• Verification IP

The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs.

• Controller
• DDR5

The DDR5RCD01 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs.

• Controller
• DDR5

MIPI DSI Transmitter IP is designed to transmit the data to the host processor.

• MIPI

Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application.

• I2C / I3C

The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication.

• I2C / I3C
• Proven at Customer FPGA/SoC
• Immdiate
• Compliance as per MIPI-I3C …

RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products …

• RISC-V

The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Comm…

• I2C / I3C

MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for …

• I2C / I3C

Provides full AVS Bus slave functionality compliant with the AVS Bus specification.

• Power Management Controller

Designed to enable efficient, high-speed communication between the SoC processor subsystem and external voltage regulators through the industry-standard AVS Bus protocol.

• Power Management Controller

MIPI A-PHY v1.0 is a physical layer communication protocol designed for automotive applications, including driver assistance, aut…

• Verification IP