Vendor: Altera Category: CXL

Compute Express Link (CXL) FPGA IP

Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.

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Overview

Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.

First FPGA to pass CXL Consortium Compliance Program (up to 32 GT/s speed).

CXL Protocol Hard IP Functionality Accelerates a Wide Range of Data-Centric Workloads

  • Accelerated Computing: CXL seamlessly connects FPGAs to accelerators and GPUs, enhancing performance in compute-intensive workloads like AI, machine learning, data analytics, and scientific simulations.
  • Memory Expansion: CXL enables FPGA-based systems to extend their memory capacity by connecting to CXL-compatible memory devices, improving performance in memory-bound applications like memory databases and large-scale data processing.
  • Data Processing: FPGAs with CXL support are used in data processing workloads, including real-time data analytics, financial modeling, and high-frequency trading, where low latency and high bandwidth are critical.

Key features

  • Fully integrated CXL IP solution with PCIe 5.0 x16 (32 GT/s) performance.
  • CXL 1.1 compliant IP that combines both hard and soft resources:
    • R-Tile Hard IP (PHY IP) reduces logic resourcing and simplifies timing closure.
    • Soft wrapper for added design flexibility and easy integration.
  • Validated with 4th and 5th Gen Intel® Xeon® Scalable Processors.
  • Compute Express Link Consortium compatible with CXL certification software (CXL_CV_app).
  • CXL protocol support: CXL.io, CXL.mem, CXL.cache.
  • Device type support: Type 1, 2, and 3.
  • CXL 1.1. IP enhanced with 2.0 features and functionality.
  • Flexible device-attached memory subsystem architecture:
    • Allows FPGA developer to mix and manage different memory types for maximum scalability and application fit.

Block Diagram

Compute Express Link (CXL) FPGA IP block diagram

Specifications

Identity

Part Number
Compute Express Link (CXL) FPGA IP
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
Contact Altera

Learn more about CXL IP core

Industry 1st CXL 4.0 Verification IP: Transforming AI and HPC Systems

Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.

Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification

Compute Express Link (CXL) is revolutionizing data center architecture, with power management emerging as a key area of innovation. Among its power-saving mechanisms, the L0p (Low Power) state plays a pivotal role in reducing energy consumption during periods of low link activity.

Demystifying CXL Memory Interleaving and HDM Decoder Configuration

Memory interleaving is a technique that distributes memory addresses across multiple memory devices or channels. Instead of storing data sequentially in one device, the system alternates between devices at a fixed granularity. It could help improve bandwidth, reduce latency, and enhance scalability. In the context of Compute Express Link (CXL), memory interleaving is facilitated by the HDM (Host-Managed Device Memory) Decoder.

Boosting AI Performance with CXL

AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter path forward. Cadence's blog, "Boosting AI Performance with CXL," outlines how CXL enables dynamic memory expansion, memory sharing, and maintains coherency across devices to eliminate bottlenecks and boost performance for processing training and inference in large-scale AI systems.

Frequently asked questions about CXL IP cores

What is Compute Express Link (CXL) FPGA IP?

Compute Express Link (CXL) FPGA IP is a CXL IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this CXL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CXL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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