Vendor: Altera Category: Ethernet

Low Latency Ethernet 10G MAC FPGA IP

The Low Latency Ethernet 10G MAC FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint.

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Overview

The Low Latency Ethernet 10G MAC FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint. The Intellectual Property (IP) core offers programmability of various features listed. This IP can be used in conjunction with the new Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

The legacy 10G Ethernet MAC FPGA IP core continues to be offered with a full feature set for applications targeting Stratix® V FPGAs, and prior FPGA families.

The 10GE MAC and PHY function with various optional features is also available as hard IP on Stratix® 10 devices with E-tiles. More details can be found at Stratix® 10 FPGA E-Tile Hard IP for Ethernet IP Core.

This FPGA IP core is designed to the IEEE 802.3–2008 Ethernet Standard, available on the IEEE website (www.ieee.org). All Low Latency 10GbE MAC FPGA IP core variations include only MAC in full-duplex mode.

Key features

MAC Features:

  • Full-duplex MAC in eight operating modes: 10G, 1G/10G, 1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G.
  • Three variations for selected operating modes: MAC TX block, MAC RX block, and MAC TX and RX blocks. A 10GBASE-R register mode on TX and RX datapaths enables lower latency.
  • Programmable promiscuous (transparent) mode.
  • Unidirectional feature specified by IEEE 802.3 (Clause 66). Priority-based flow control (PFC) with programmable pause quanta, supporting two to eight priority queues.
  • Interfaces:
    • Client-side: 32-bit Avalon® streaming interface (Avalon-ST).
    • Management: 32-bit Avalon-MM interface.
    • PHY-side: 32-bit XGMII for 10GbE, 16-bit GMII for 2.5GbE, 8-bit GMII for 1GbE, or 4-bit MII for 10M/100M.
  • Frame Structure Control Features:
    • Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).
    • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath.
    • Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications. Supports programmable IP.
    • Ethernet flow control using pause frames.
    • Programmable maximum length of transmit (TX) and receive (RX) data frames up to 64 kilobytes (KB).
    • Preamble passthrough mode on TX and RX datapaths, which allows user-defined preamble in the client frame.
    • Optional padding insertion on the TX datapath and termination on the RX datapath.
  • Frame Monitoring and Statistics:
    • Optional CRC checking and forwarding on the RX datapath.
    • Optional statistics collection on TX and RX datapaths.
  • Optional Timestamping, Specified in IEEE 1588v2, for the Following Configurations:
    • 10GbE MAC with 10GBASE-R PHY IP core.
    • 1G/10GbE MAC with 1G/10GbE PHY IP core.
    • 1G/2.5GbE MAC with 1G/2.5G Multirate Ethernet PHY IP core.
    • 1G/2.5G/10GbE MAC with 1G/2.5G/10G (MGBASE-T) Multirate Ethernet PHY IP core.
    • 10M/100M/1G/10GbE MAC with 10M-10GbE PHY IP core.
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP core.

Block Diagram

Low Latency Ethernet 10G MAC FPGA IP block diagram

Specifications

Identity

Part Number
Low Latency Ethernet 10G MAC FPGA IP
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
Contact Altera

Learn more about Ethernet IP core

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Frequently asked questions about Ethernet IP cores

What is Low Latency Ethernet 10G MAC FPGA IP?

Low Latency Ethernet 10G MAC FPGA IP is a Ethernet IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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