DMA IP cores enable efficient data movement and event handling in embedded systems, reducing CPU load and improving overall SoC performance. These semiconductor IP blocks are widely used in MCUs, processors, multimedia platforms, and real-time control systems.
Compare DMA and interrupt controller IP with configurable channels, low-latency transfers, bus integration, and scalable interrupt management for advanced SoC architectures.
AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Descriptors
The DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI…
The MIPS I8500™ Multi-Processing System (MPS) builds on a long history of high performance multi-threaded and multiprocessor IP p…
AHB Scatter-Gather DMA Controller
The eSi-SG-DMA core can be used to implement 1D and 2D memory-to-memory, memory-to-peripheral, peripheral-to-memory and periphera…
AXI4-Stream to/from AXI Memory Map - AXI Memory Map Conversion to AXI4-Stream, 16 Channels
The DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the a…
AXI4-Stream to/from AXI Memory Map - AXI4-Stream Conversion to AXI Memory Map, 16 Channels
The DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to …
AMBA AHB 4 Channel DMA Controller
The AHB 4 Channel DMA Controller is a multiple-channel direct memory access controller.
AHB Single Channel DMA Controller
The DMA is a configurable single channel direct memory access controller.
SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces
The DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers.
1 - 16 Multi-Channel High Performance DMA Controller
DTI_DMA control the DMA transfers data between different points in the memory space without intervention of the CPU.
Direct Memory Access Controller
The uDMA (Micro Direct Memory Access) controller serves as a hardware approach for direct data transfers between peripherals/memo…
The Scatter-Gather DMA Engine Verification IP (VIP) is designed to validate the functionality and performance of scatter-gather D…
Data Movement Engine - Turnkey network compute subsystem for data movement applications.
Physical AI platforms interpret their surroundings using a diverse array of sensors, generating data that must be seamlessly tran…
Direct memory access (DMA) controller
The Arm CoreLink DMA-350 direct memory access (DMA) controller offloads memory movement tasks from the CPU to improve system perf…
AXI/AXI4 compliant - Optional Scatter/Gather Direct Memory Access (DMA)
AHB Single Channel DMA Controller
The AHB Single Channel DMA Controller core is a configurable single channel direct memory access controller.
The Multi-Channel Direct Memory Access (MCDMA) Controller is designed to improve microprocessor system performance by allowing ex…
The AXI MCDMA facilitates large data migration, offloading the task from the embedded processor.
The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core that provides high-bandwidth direct memory access bet…
The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between memory and AXI4-Stream-type target…