Overview
The Arm CoreLink DMA-350 direct memory access (DMA) controller offloads memory movement tasks from the CPU to improve system performance and energy-efficiency. It includes support for scatter gather, 2D transformations, memory to memory, memory to peripheral (and vice versa) transfers.
CoreLink DMA-350 is a highly configurable IP based on the AMBA AXI5 protocol with support for eight channels, two AXI manager interfaces, Arm TrustZone technology, and other advanced features. This DMA controller pairs well with the Cortex-M55 processor in endpoint AI systems to populate the tightly coupled memory (TCM) with data efficiently for ML and signal processing. CoreLink DMA-350 also supports integration into systems based on Arm Cortex-A and Cortex-R CPUs and can be easily programmed via an AMBA 4 APB interface.
Learn more about DMA IP core
Some systems have very clever peripherals and they are not just there to fill up the available silicon space. So, use the peripheral system to your advantage. If you have a DMA engine and need to copy large amounts of data about then use it! You can either have the CPU go off and do something else in parallel during the transfer time or, if nothing else needs doing, put it to sleep and wake it up when the data is in place.
This whitepaper describes the details of a newly developed processor design within the common ARM Cortex applications profile
This white paper will examine the key differences between the ARM9E processor family and the Cortex-R4 processor.
The ARM® Cortex™-R4 processor enables a wide range of deeply-embedded applications to be implemented with reduced system and development cost. Product applicability includes hard-disk drives, networking products, wireless and automotive applications.
This paper shows, by example, typical problems encountered by embedded systems programmers and how the new ARM® CoreSight™ technology can be deployed to give the developer the maximum visibility in to the chip’s operations and malfunctions
There are many IP’s today . These IP’s can be simple IP’s like Timer to complex IP’s like Accelerators. In Most of the cases IP’s are Integrated in standard way. There are cases where you have the option of Integrating it differently. This goes un-noticed or unable to be implemented due to time constraints. One such IP that would be discussed in this paper is DMA . This paper tries to explain idea of Integrating Direct Memory access(DMA) and Interrupt Control Unit(ICU) differently but final implementation requires some changes in IP. There is a possibility that alternate design explained below may be already implemented.
