SG DMA Controller, 1-16 DMA Channels, AHB5 Master Interface

The DB-DMAC-MC-AHB5 & DB-DMAC-MC-AHB-Lite Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers. The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with a unified AHB Master Read/Write interconnects. The DB-DMAC-MC-AHB excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, and 16. Please contact the endor about our configurable DB-DMAC-MC-AHB with 1 to 256 DMA Channels.

• 1 - 16 Multi-Channel High Performance DMA Controller Engines:
  • High-Speed Finite State Machine Control
  • Up to 16 DMA transfers operational in parallel
  • High Throughput to/from Memory via AMBA AHB on both small and large data sets
  • Dual-Port, Single-Clock FIFO, user parameterized in Depth x Width.
  • Optional Dual-Port, Dual-Clock FIFO design
  • Optional external single memory interface for all DMA Multi-Channels
  • Fixed number of DMA Multi-Channel releases at lower licensing cost
• Contact Digital Blocks about our configurable DB-DMAC-MC-AHB with 1 to 256 DMA Channels.
• DMA releases with either AMBA AHB5 or AHB-Lite supported
• Supports following DMA transfers:
  • Memory-to-Memory
  • Memory-to-Peripheral
  • Peripheral-to-Memory
  • Peripheral-to-Peripheral
• Scatter Gather List (SGL):
  • processing of linked-list Descriptor nodes
  • supports non-contiguous data block transfers to a contiguous segment of memory and vice versa
• Variety of User DMA Transfer Control:
  • Link-List Processor for Autonomous & Chained Block Transfers (SGL)
  • CPU Software or external Hardware initiated transfers
• Targets CPU DMA & PCIe DMA Controller in Linux environment as well as applications with standard peripherals or unique peripheral data transfer requirements
• Arbiter – Round Robin (priority Arbitration Modes available – contact Digital Blocks)
• Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024.
• Programmable Data Burst Capability: 1, 4, 8, 16 and up to 256 via AHB
• Interrupt Controller – Signaling DMA Status - Transfer Done & Diagnostics
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

• Verilog RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.