Vendor: Digital Blocks, Inc. Category: DMA

SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces

The DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers.

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Overview

The DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers. The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with user selectable AMBA AXI4 / AXI3 Master Read/Write interconnects. The DB-DMAC-MC-AXI excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, 16. Please contact the vendor about our configurable DB-DMAC-MC-AXI with 1 to 256 DMA Channels.

Key features

  • 1 - 16 Multi-Channel High Performance DMA Controller Engines:
    • High-Speed Finite State Machine Control
    • High Throughput to/from Memory & Peripherals via AMBA AXI4 / AXI3 on both small and large data sets
    • Dual-Port, Dual-Clock FIFO, user parameterized in Depth x Width
    • Optional Dual-Port, Single-Clock FIFO design
  • Up to 16 DMA transfers in parallel active
  • Hardware or Software Initiated Transfers
  • Link-List Processor for Autonomous & Chained Block Transfers
  • Scatter / Gather – supports non-contiguous data block transfers to a contiguous segment of memory and vice versa
  • Arbiter with variety of Arbitration Modes including Quality of Service (QoS) and low-latency
  • Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024. Data re-alignment matching interfaces with different data widths
  • Programmable Data Burst Capability: 1, 4, 8, 16 on AXI4/AXI3 Interfaces. Up to 256 on AXI4
  • Interrupt Controller – Signaling DMA Transfer Done & Diagnostics
  • AXI DMA Backbone or PCIe DMA Engine
  • Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

Block Diagram

DB-DMAC-MC-AXI block diagram

What’s Included?

  • Verilog RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Specifications

Identity

Part Number
DB-DMAC-MC-AXI
Vendor
Digital Blocks, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Digital Blocks, Inc.

Learn more about DMA IP core

DMA IP Integration

There are many IP’s today . These IP’s can be simple IP’s like Timer to complex IP’s like Accelerators. In Most of the cases IP’s are Integrated in standard way. There are cases where you have the option of Integrating it differently. This goes un-noticed or unable to be implemented due to time constraints. One such IP that would be discussed in this paper is DMA . This paper tries to explain idea of Integrating Direct Memory access(DMA) and Interrupt Control Unit(ICU) differently but final implementation requires some changes in IP. There is a possibility that alternate design explained below may be already implemented.

Moving to AMBA® 5? Your AMBA® 4 IP Can Still Come With You

As SoC architectures adopt AMBA® 5 fabrics and components, many proven IP blocks still rely on AMBA® 4 or earlier interfaces. That creates a common integration problem: how do designers connect newer AMBA® 5 system components to existing IP without redesigning the IP or replacing verified blocks?

Frequently asked questions about DMA IP

What is SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces?

SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces is a DMA IP core from Digital Blocks, Inc. listed on Semi IP Hub.

How should engineers evaluate this DMA?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DMA IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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