Vendor: eSi-RISC Category: DMA

AHB Scatter-Gather DMA Controller

The eSi-SG-DMA core can be used to implement 1D and 2D memory-to-memory, memory-to-peripheral, peripheral-to-memory and periphera…

Overview

The eSi-SG-DMA core can be used to implement 1D and 2D memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral data transfers, with scatter and gather functionality.

As well as linked-list based memory copies, the DMA can be programmed to perform memory set/zero, endian conversion, deinterleaving, matrix transpose and other transforms as well as CRC and IP checksum calculation during transfers.

The core features 3 AMBA AHB-lite interfaces, to easily be integrated in to any CPU subsystem.

Key features

  • Memory-based, linked-list transfer descriptors.
  • 3 descriptor sizes to balance functionality and setup overhead.
  • Configurable number of channels.
  • Configurable number of peripherals (up to 64).
  • Programmable X and Y count, increment, access size and burst length.
  • CRC and IP checksum calculation.
  • AMBA 3 AHB-lite slave interface for control register access.
  • Dual AMBA 3 AHB-lite master interfaces for simultaneous read and write.

What’s Included?

  • Verilog RTL
  • Testbench
  • Simulation and synthesis scripts
  • Documentation
  • C API

Specifications

Identity

Part Number
eSi-SG-DMA
Vendor
eSi-RISC
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: UK

Frequently asked questions about DMA IP

What is AHB Scatter-Gather DMA Controller?

AHB Scatter-Gather DMA Controller is a DMA IP core from eSi-RISC listed on Semi IP Hub.

How should engineers evaluate this DMA?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DMA IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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