Overview
The eSi-SG-DMA core can be used to implement 1D and 2D memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral data transfers, with scatter and gather functionality.
As well as linked-list based memory copies, the DMA can be programmed to perform memory set/zero, endian conversion, deinterleaving, matrix transpose and other transforms as well as CRC and IP checksum calculation during transfers.
The core features 3 AMBA AHB-lite interfaces, to easily be integrated in to any CPU subsystem.
Learn more about DMA IP core
There are many IP’s today . These IP’s can be simple IP’s like Timer to complex IP’s like Accelerators. In Most of the cases IP’s are Integrated in standard way. There are cases where you have the option of Integrating it differently. This goes un-noticed or unable to be implemented due to time constraints. One such IP that would be discussed in this paper is DMA . This paper tries to explain idea of Integrating Direct Memory access(DMA) and Interrupt Control Unit(ICU) differently but final implementation requires some changes in IP. There is a possibility that alternate design explained below may be already implemented.
By Dany Nativel, Jacko Wilbrink and Tim Morin
As SoC architectures adopt AMBA® 5 fabrics and components, many proven IP blocks still rely on AMBA® 4 or earlier interfaces. That creates a common integration problem: how do designers connect newer AMBA® 5 system components to existing IP without redesigning the IP or replacing verified blocks?
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
This work investigates a novel threat model in which standard cells are considered untrusted. Our proposed threat model provides the design house with a tampered standard cell library. The intended netlist is synthesized and implemented using the tampered library.
