The Helion Fast Hash core family implements the NIST approved SHA-1, SHA-256, SHA-384 and SHA-512 secure hash algorithms to FIPS …
- Hash / MAC
Cryptography IP cores provide hardware-based security functions for protecting data, communications, and digital assets in modern SoC and ASIC designs. By offloading cryptographic operations from software, these IP cores deliver higher performance, lower latency, improved energy efficiency, and stronger resistance to security attacks.
This category includes Symmetric Cryptography, Public Key Cryptography, Post-Quantum Cryptography (PQC), Hash / MAC, and Random Number Generator (RNG) IP solutions. Available implementations may support algorithms such as AES, ChaCha20, RSA, ECC, ML-KEM, ML-DSA, SHA-2, SHA-3, HMAC, CMAC, and true or deterministic random number generation technologies required for secure key management and authentication.
This catalog enables semiconductor engineers to evaluate and compare Cryptography IP from leading vendors based on supported algorithms, security certifications, throughput, latency, power consumption, silicon area, side-channel resistance, quantum-safe capabilities, and semiconductor process node compatibility.
The Helion Fast Hash core family implements the NIST approved SHA-1, SHA-256, SHA-384 and SHA-512 secure hash algorithms to FIPS …
The Standard AES core family is our mid-rate solution, aimed at applications which require a few hundred Mbps throughput, whilst …
The Helion Tiny Hash Core family for ASIC offers a combination of high functionality and low resource usage for lower data rate a…
The Helion ARC4 core implements the Alleged RC4 stream cipher algorithm.
Compliant to NIST FIPS PUB 197
ML-KEM-X Post-Quantum Cryptography Core
Scalable, Parameterized, ACVP-Validated Key Encapsulation IP for FIPS 203 Compliance
SmartDV’s AES ( Encryption Standard) IP core is a silicon-proven, hardware-accelerated encryption solution engineered for SoC app…
Cryptographic engine using the DES, Triple-DES or AES
The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
Security Hash, SM3 Hash and HMAC Engine
The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512), …
On-the-fly decryption engine FRTDEC allows to decrypt on-the-fly AXI traffic based on the read request address information.
Asymmetric cryptographic accelerator
The ACrypto Engine is an asymmetric cryptographic accelerator suitable for embedded application.
Symmetric Cryptographic Intel® FPGA IP
The Symmetric Cryptographic Intel® FPGA IP is a hard IP core implementing AES and SM4 encryption and decryption.
Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
PQCryptoLib-Embedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
Standalone stateful hash-based signatures software library
The SHSlib is a standalone stateful hash-based signatures software library, which provides signature verification for stateful ha…
AES - Encrypts sensitive data to ensure secure communication and transactions
AES ( Encryption Standard) is a widely-used encryption algorithm designed to secure sensitive data.
SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard.
AES-256SS IP specializes in ultra-high throughput and ultra-low latency.
High-speed Inline Cipher Engine
The ICE-IP-338 (EIP-338) Inline Cipher Engine is a scalable, high-performance, multi-stream inline cryptographic engine that offe…
Inline cipher engine with AXI, for memory encryption
Modern computing architectures must address increasing concerns regarding off-chip data confidentiality.
Inline memory encryption engine, for FPGA
IME-IP-340 Inline Memory Encryption (IME) Engine provides just-in-time encryption, decryption and authentication for all memory r…