True Random Number Generators for Truly Secure Systems
Random numbers form the basis, or root, of most security systems. Yet the methods for generating random numbers vary widely in practice as well as efficacy.
Vendor:
Synopsys, Inc.
Category:
Random Number Generator
True Random Number Generator Core
True Random Number Generators (TRNGs) are required in many applications such as wired and wireless networking, IoT, automotive, g…
Overview
True Random Number Generators (TRNGs) are required in many applications such as wired and wireless networking, IoT, automotive, government and military communications, and content protection. TRNGs are used to generate keys, initialization vectors and nonces used in many security standards. The Internet of Things (IoT) is a fast-growing market where data can easily be intercepted and devices can be hacked, especially if weak RNGs are selected. Rigid compliance with the latest standards like NIST, BSI, and certifications including FIPS 140-2/140-3, Common Criteria and OSCCA can provide protection against malicious attacks and alleviate concerns about security backdoor issues such as those widely reported in the media recently.
The security strength of many systems and applications is dependent on the quality of random number generators. Many cryptographic operations require a source of random numbers primarily in the creation of cipher keys and initial values for counters and protocol parameters. The vendor's silicon proven digital True Random Number Generators combine a whitening circuit with a noise source that provides automatic seeding of the random number stream and an ongoing source of entropy to the core. The cores are therefore classified as non-deterministic random bit generators using the terminology preferred by NIST. The noise source does not depend on process specific circuitry and is therefore very portable across different ASIC and FPGA fabrication technologies.
Key features
- Designed for compliance with FIPS 140-2/140-3 and OSCCA certifications
- Customer configurable
- Wide system clock dynamic range
- Redundant internal seed generators
- Selectable number of seed generators: 6 or 8
- Automatic and manual reseeding
- Two independent background automatic reseed modes
- Shift register compatible output stream for auxiliary uses
- Various interfaces supported: memory mapped (AXI/AHB/APB), serial random bit stream, and nonce interface compatible with Synopsys HDCP Content Protection ESMs
Specifications
Identity
Part Number
dwc_trng
Vendor
Synopsys, Inc.
Type
Silicon IP
Security
RNG Type
TRNG
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Random Number Generator IP core
Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Reference Verification Methodology (RVM)
Writing individual tests is impractical for today’s large, complex designs because the state space and number of test conditions is simply too large to code by hand, leading to insufficient test coverage
Generating AMD microcode stimuli using VCS constraint solver
As microprocessor designs have grown considerably in complexity, the use of hand-written directed tests in verification has dwindled. In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
Accelerated SoC Verification with Synopsys Discovery VIP for the ARM AMBA 4 ACE Protocol
This paper describes how a reference verification platform built with the Discovery VIP for the AMBA ACE protocol can be utilized to accelerate the verification of multi-core SoCs. Also highlighted are Synopsys verification technologies like Discovery Visualization Environment (DVE) and Protocol Analyzer for advanced debug of the AMBA 4 AXI/ACE protocols.
Functional Coverage Analysis for IP Cores and an Approach to Scaledown Overall Simulation Time
This paper presents functional coverage analysis automation and an approach to scale down overall simulation time. It is well known that functional verification of configurable IP cores is a real challenging task in any digital design development. Consequently, it is necessary to develop new methodologies to improve the quality of functional verification and also to decrease the time for regression convergence.
Advanced Power Management in Embedded Memory Subsystems
This paper addresses minimizing low-power design complexity with power, performance and density optimized IP. It covers the power problem, and the complexity of designing with multiple power domains in SoC designs that contain embedded memory. The paper includes the trade-offs and benefits of various power management features as well as the implementation of the design for superior testability by providing optimal test resource partitioning.
Frequently asked questions about Random Number Generator IP cores
What is True Random Number Generator Core?
True Random Number Generator Core is a Random Number Generator IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this Random Number Generator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Random Number Generator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.