AES-GCM Authenticated Encrypt/Decrypt Engine
The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
- AES
Cryptography IP cores provide hardware-based security functions for protecting data, communications, and digital assets in modern SoC and ASIC designs. By offloading cryptographic operations from software, these IP cores deliver higher performance, lower latency, improved energy efficiency, and stronger resistance to security attacks.
This category includes Symmetric Cryptography, Public Key Cryptography, Post-Quantum Cryptography (PQC), Hash / MAC, and Random Number Generator (RNG) IP solutions. Available implementations may support algorithms such as AES, ChaCha20, RSA, ECC, ML-KEM, ML-DSA, SHA-2, SHA-3, HMAC, CMAC, and true or deterministic random number generation technologies required for secure key management and authentication.
This catalog enables semiconductor engineers to evaluate and compare Cryptography IP from leading vendors based on supported algorithms, security certifications, throughput, latency, power consumption, silicon area, side-channel resistance, quantum-safe capabilities, and semiconductor process node compatibility.
AES-GCM Authenticated Encrypt/Decrypt Engine
The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Programmable Advanced Encryption Standard Engine
The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Advanced Encryption Standard Engine
The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
The SHA-3 module implements the SHA3-512, SHA3-384, SHA3-256 and SHA3-224 hash algorithms and the SHAKE128 and SHAKE256 extendabl…
SHA-512, SHA-384, SHA512/256 and SHA-512/224
The SHA-512 module implements the SHA-512, SHA-384, SHA-512/256 and SHA-512/224 hash algorithms specified in FIPS PUB 180-4, the …
The SHA-256 module implements both the SHA-256 and SHA-224 hash algorithms specified in FIPS PUB 180-4, the Secure Hash Standard.
AES-GCM IP Core for 40Gbit/sec packet data
This state of the art implementation of AES-GCM achieves 40Gbit/sec performance on Virtex 5 FPGAs.
Duplex AES-GCM at 10Gbit/sec for OTN
This state of the art implementation of the AES-GCM algorithm provides privacy and authentication and achieves 10Gbit/sec perform…
This core extends the Algotronix G3 Encryption Standard (AES) core by providing a secure, standardized method for loading cryptog…
High speed low latency AES-GCM pipeline, 100Gbps
The AES-IP-61 (EIP-61) is IP for accelerating AES-GCM based cryptographic solutions.
TRNG fully compliant with NIST 800-22
The eSi-TRNG is a high quality implementation of a True Random Number Generator fully compliant with latest NIST 800-22.
eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies.
RSA Public Key Cryptography Exponentiation Accelerator
The modular exponentiation accelerator IPX-RSA is an efficient arithmetic coprocessor for the RSA public-key cryptosystem.
SMIC 0.18um Random Code Generator
SMIC18_RCG_02 is to generate random code.
LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption.
The Helion Modular Exponentiation core performs the Z = YE mod M computation which is at the heart of many commonly used Public-K…
High-Speed AES Encryption Cores
D’Crypt’s AES core is a high-performance pipelined implementation of the AES (Rijndael) encryption algorithm.
SHA-1 Hash Function Calculation
The ALSHA core is the VHDL model of the processor that performs SHA-1 hash function calculation.
DES Encryption and Decryption Processor
The IP-ALDES core is the VHDL model of the processor, that performs DES encryption and decryption.
NIST’s ASCON Lightweight Crypto Algorithm Accelerator
The ASCON-IP-41 is an efficient implementation of NIST’s lightweight crypto algorithm family ASCON.