RISC-V IP Listing

The SiFive U54 Standard Core is a single-core instantiation of the world's first RISC-V application processor, capable of support…

• RISC-V

The SiFive S76-MC Standard Core is a high-performance 64-bit quad-core embedded processor which is fully-compliant with the RISC-…

• CPU

The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA.

• CPU

The SiFive S54 Standard Core is a 64-bit embedded processor that is fully-compliant with the RISC-V ISA.

• RISC-V

The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA.

• RISC-V

The SiFive E76-MC Standard Core is a high-performance quad-core 32-bit embedded processor which is fully-compliant with the RISC-…

• CPU

The SiFive E76 Standard Core is a high-performance 32-bit embedded processor which is fully-compliant with the RISC-V ISA.

• CPU

The SiFive E34 Standard Core adds single-precision floating-point to the SiFive E31 Standard Core, the worldÃ?¢Ã?Â?Ã?Â?s most de…

• RISC-V

The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capa…

• MCU

The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power.

• RISC-V

The SiFive U84 Standard Core is a single-core instantiation of our most scalable out-of-order RISC-V application processor, and i…

• CPU
• Now
• RISC-V ISA

IOb-SoC is a RISC-V SoC template written in Verilog, which users can download for free, modify, simulate and implement in FPGA or…

• RISC-V

The 32-bit A27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instruction…

• CPU

The 64-bit AX27 is a 5-stage processor that supports the latest RISC-V specification, including “G“ (“IMAFD”) standard instructio…

• CPU

Codasip Studio is a set of Electronic Design Automation (EDA) tools for processor design and customization.

• CPU
• in production
• now

Ceva-MotionEngine is Ceva’s core sensor processing software system and is the product of over 20 years of experience developing s…

• Edge AI Accelerator

AndesCore™ AX25MP 64-bit multicore CPU IP is based on AndeStar™ V5 architecture.

• CPU

AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture.

• CPU

AndesCore™ D25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of…

• CPU

AndesCore™ N25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of…

• CPU