Vendor: Sifive, Inc. Category: CPU

E20 Smallest, most efficient RISC V Ccore

The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power.

Overview

The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines.

Further optimize the E2 Core for the smallest area using SiFive Core Designer.

Key features

  • RISC-V ISA - RV32IMC
  • Machine Mode only
  • 2-stage pipeline
  • System Port for external memory accesses
  • Core Local Interrupt Controller (CLIC) with 32 interrupts
  • Advanced debug with 4 hardware breakpoints/watchpoints
  • 1.22/1.84 DMIPS/MHz (Legal/Best Effort)
  • 2.51 CoreMark/MHz

Block Diagram

Specifications

Identity

Part Number
E20
Vendor
Sifive, Inc.
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about CPU IP cores

What is E20 Smallest, most efficient RISC V Ccore?

E20 Smallest, most efficient RISC V Ccore is a CPU IP core from Sifive, Inc. listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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