Overview
The SiFive S76-MC Standard Core is a high-performance 64-bit quad-core embedded processor which is fully-compliant with the RISC-V ISA.
The S76-MC is ideal for latency-sensitive applications in domains such as storage and networking that require high-throughput, 64-bit memory addressability, and have real-time constraints (e.g. Enterprise Storage, In-storage Compute, 5G Base Stations, SLAM processing, etc.)
Learn more about CPU IP core
In a demonstration-only system, the companies showed the ability to run the modern Gemma4-E2B LLM model using ROCm 10.0 on SiFive servers powered by the SiFive Performance™ P870-D CPUs acting as the head node, and AMD Radeon™ AI PRO R9700 GPUs driving the inference offload.
The broader RISC-V standards process continues to deliver innovation that responds dynamically to evolving market needs. If you didn’t see the announcement, in an important milestone for the open hardware ecosystem, the RISC-V Board of Directors officially ratified the S-mode Physical Memory Protection (SPMP) version 1.0 specification on August 20, 2026.
Powered by SiFive’s latest RISC-V CPU technology, the new development platform enables hands-on software porting, workload tuning, and validation testing for hyperscaler customers and ecosystem partners
We’re thrilled to announce the launch of the SiFive Kernel Library or SKL (pronounced “skill”), an open-source collection of highly-optimized computational routines for the RISC-V Vector ISA (RVV) and its various extensions, including SiFive’s matrix engines.
SiFive is evolving the building blocks of RISC-V-based IP that are reimagining and democratizing every computing platform. We take a closer look at the new Performance P570 Gen 3 and its next-gen applications.
Purpose-built for demanding edge AI, high-end consumer, and commercial IoT applications, the P570 Gen 3 delivers a large leap in performance compared to the popular P550 Gen 1, and also provides the most modern RVA23 ISA profile support.
