Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Andes Technology Corp.
Category:
CPU
64-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ AX25MP 64-bit multicore CPU IP is based on AndeStar™ V5 architecture.
Overview
AndesCore™ AX25MP 64-bit multicore CPU IP is based on AndeStar™ V5 architecture. It supports RISC-V standard 'IMAC-FD' extensions, Andes contributed DSP/SIMD 'P' extension (draft), user-level interrupt 'N' extension, and Andes performance/ functionality enhancements such as instructions for faster memory accesses, faster branch handling, and Andes Custom Extension™ (ACE) to add user-defined instructions. It features MMU for Linux based applications, branch prediction for efficient branch execution, level-1 instruction/data caches and local memories for low-latency accesses.
The AX25MP symmetric multiprocessor supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. Andes Coherence Unit (ACU) manages level-1 cache coherence, including I/O coherence for cacheless bus masters, and duplicated L1 tag to screen allocated lines for snoop queries. Other AX25MP features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™, StackSafe™ for software quality improvement, and QuickNap™, PowerBrake, and WFI for power management.
Key Features and Performance
AndeStar™ V5 Architecture
| Key Features | Benefits |
|---|---|
| RISC-V RV64IMACFDBP instructions |
|
| 64-bit CPU architecture | Enabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs |
| RISC-V P-extension (draft) DSP/SIMD instructions with versatile operations | Boost the performance of voice, audio, image and signal processing |
| RISC-V single and double precision floating point instruction | Accelerate the processing of high precision arithmetic |
| RISC-V bit-manipulation instructions, including the Zba, Zbb, Zbc and Zbs extensions | Benefits codes with bit-wise operations |
| Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
| Andes Custom Extension™ (ACE) option to create customized instructions for software acceleration |
|
| 16/32-bit mixable instruction format | For compact code density |
| 32 general-purpose registers | For better code size and performance |
| Machine (M), User (U) and Supervisor (S) Privilege levels | For Linux and advanced operating systems with protection between kernel and user programs |
CPU Core
| Key Features | Benefits |
|---|---|
| 3.55 Coremark/MHz, 2.14 DMIPS/MHz* | Superior performance-per-MHz |
| 5-stage pipeline, with a full-cycle reserved for critical SRAM accesses | Superior performance-efficiency, while allowing for high speeds |
|
Extensive branch prediction features
|
|
|
Memory Management Unit
|
|
| Physical Memory Protection (PMP), 16 regions | Basic read/write/execute memory protection with minimum cost |
| Performance monitors | Program code performance tuning |
| StackSafe™ hardware stack protection |
|
|
Multiplier options
|
Option to choose between speed and area according to application's requirements |
| PowerBrake technology | Performance throttling to digitally reduce power consumption |
* AndeSight v500, DMIPS/MHZ follow Dhrystone’s no-inline ground rules, best performances
Memory Subsystems
Platform-Level Interrupt Controller (PLIC)
| Key Features | Benefits |
|---|---|
|
Implements RISC-V PLIC specification
|
Allow individual interrupts to be serviced and prioritized without sharing |
|
Enhanced interrupt features
|
|
Debug Support
| Key Features | Benefits |
|---|---|
| Implements RISC-V debug specifications | Supported by industry debug tool suppliers |
| JTAG Debug Port | Industry-standard support |
| Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
| Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
| Key Features | Benefits |
|---|---|
|
Level-1 I-Cache & D-Cache
|
|
|
ILM & DLM
|
|
| Soft-error protection: ECC or parity for I-Cache and D-Cache, ILM and DLM with SRAM interface | Code and data integrity protection |
|
Level-2 cache
|
|
|
Multicore Cache Coherence
|
|
| Bus manager port: AXI 64 or 128-bit data, 32 to 64-bit address | User-selectable bus interface for optimal efficiency |
| Bus subordinate port: AHB with 64-bit data, for ILM/DLM accesses | Efficient data transfer between CPU and SoC managers |
| Core/bus clock ratio of N:1 | Simplified SoC integration |
Key features
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
- AndeStar™ V5 Instruction Set Architecture (ISA). Compliant to RISC-V ISA IMACFDN, with Andes performance/functionality extensions
- Floating point extension DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
- 64-bit architecture for memory space over 4GB
- 16/32-bit mixable instruction format for compacting code density
- Branch predication to speed up control code
- Return Address Stack (RAS) to speed up procedure returns
- Memory Management Unit (MMU) and Physical Memory Protection (PMP)
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
Block Diagram
AndesCore™ AX25MP block diagram
Applications
- Machine/Deep learning acceleration
- High performance solid state drives
- Large-scale network controllers
- Industrial Automation
Specifications
Identity
Part Number
AndesCore™ AX25MP
Vendor
Andes Technology Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
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Frequently asked questions about CPU IP cores
What is 64-bit Multiprocessor with Level-2 Cache-Coherence?
64-bit Multiprocessor with Level-2 Cache-Coherence is a CPU IP core from Andes Technology Corp. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.