Vendor: Sifive, Inc. Category: CPU

U54 Linux-capable RISC V application processor

The SiFive U54 Standard Core is a single-core instantiation of the world's first RISC-V application processor, capable of support…

Overview

The SiFive U54 Standard Core is a single-core instantiation of the world's first RISC-V application processor, capable of supporting full-featured operating systems such as Linux.
The U54 is ideal for low-cost Linux applications such as IoT nodes and gateways, point-of-sale, and networking.

Key features

  • Fully compliant with the RISC-V ISA specification
  • RV64GC U54 Application Core
    • 16KB L1 I-cache with ECC
    • 16KB L1 D-cache with ECC
    • 8 Region Physical Memory Protection
    • 48 Local Interrupts per core
    • Sv39 Virtual Memory support with 38 Physical Address bits
  • Integrated 128KB L2 Cache with ECC
  • Real-time capabilities
    • Both the L1 Instruction Cache and the L2 Cache can be configured into high speed deterministic SRAMs
    • CLINT for multi-core timer and software interrupts
    • PLIC with support for up to 128 interrupts with 7 priority levels
    • Debug with instruction trace
  • U54 Performance
    • 2.87/1.7 DMIPS/MHz (Best Effort/Legal)
    • 2.75 CoreMark/MHz

Block Diagram

Specifications

Identity

Part Number
U54
Vendor
Sifive, Inc.
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about CPU IP core

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Frequently asked questions about CPU IP cores

What is U54 Linux-capable RISC V application processor?

U54 Linux-capable RISC V application processor is a CPU IP core from Sifive, Inc. listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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