Vendor: Codasip Category: CPU

Processor Development Toolset

Codasip Studio is a set of Electronic Design Automation (EDA) tools for processor design and customization.

Overview

Codasip Studio is a complete set of Electronic Design Automation (EDA) tools for processor design and customization. The level of automation is unmatched on the market, and produces fast and efficient results.

Our approach at Codasip is to automate the development of processor cores by using a high-level description in the CodAL processor description language and generating the design implementation, verification environment, virtual system prototype, and a complete software toolchain using Codasip Studio.

In addition to its design capabilities, Codasip Studio includes powerful multiprocessor programming, debugging and profiling features, enabling the development of complex processor designs with ease.

Codasip Studio is built upon open standards and software including Eclipse, LLVM, Verilog, SystemVerilog, and UVM.

Key features

  • A unified development model describing the processor in a single CodAL description
  • High performance processor synthesis
  • Complete UVM verification environment
  • Advanced profiling and analysis
  • Compatible with Codasip RISC-V cores

Block Diagram

Benefits

  • By creating a high-level processor description in CodAL and automatically generating virtual prototypes, an SDK, RTL and a verification environment there is hugely reduced design time and cost.
  • CodAL allows adding application-specific instructions natively to the processor pipeline well above traditional processor extensible approaches.
  • Once an instruction-accurate model of the processor is available it is possible to generate an SDK to allow embedded software teams to develop, debug and test their code well ahead of silicon availability.
  • Codasip Studio generates human readable RTL.
  • A generated SystemVerilog UVM environment allows verification of the RTL against an instruction accurate reference model.

Applications

  • Any form of customizing Codasip RISC-V cores developed using Studio such as creating custom instructions.
  • Creating special processor architectures for specialized applications such as security, DSP, AI or imaging

Specifications

Identity

Part Number
Codasip Studio
Vendor
Codasip
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Germany

Learn more about CPU IP core

Codasip announces strategic pivot and divestiture

Codasip today announced a strategic evolution of its business to focus on the rapidly growing need for cyber-resilient semiconductor architectures and semiconductor System on Chips (SoCs). In conjunction with this change, Codasip is also announcing the divesture of its low-end RISC-V processor design business to a public US semiconductor company.

Codasip board initiates an expedited process to sell the company

Codasip, the European RISC-V leader, announced today an accelerated process to sell the company. Codasip has been awarded several grants and equity funding from various bodies of the European Union (EU) and national authorities totaling over €119 million, most of which is still to be received by the company in due course. In addition, the company estimates the follow-on phases of the grants will total a further €210 million for a total of €329 million, and the company is part of new consortiums and projects that can bring in an additional €51 million or more in future financing.

Frequently asked questions about CPU IP cores

What is Processor Development Toolset?

Processor Development Toolset is a CPU IP core from Codasip listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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