Low Power 1-22G PCIe Gen4 / SAS4 PHY on TSMC CLN16FFC

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS) capable of signaling at multiple data rates. The PHY supports multi-protocol market needs including a wide range of ac-coupled high-speed serial communication standards requiring serial Clock Data Recovery (CDR). Analog Bits’proprietary and industry leading PLL technology in combination with sophisticated circuit techniques and innovative IO design makes this macro an extremely area and power efficient solution.

The PHY includes a PCIe PCS, while featuring an additional interface capability that allows integration with other customer-designed serial protocol PCS layers at any baud rate up to 22.5Gbps. The PMA is delivered as a hard macro while the fully-synthesizable soft PCS includes performing all necessary calibration and self-test functions. The universal PHY architecture allows forming arbitrarily wide efficient links by being independent of the need for a common CMU.

• Industry leading low power PMA macro – 184mW per lane at 22.5Gbps (8.2mW/Gbps) and 108mW per lane at 16Gbps (6.75mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
• Compact form factor – 0.145 mm2 total active area per lane
• Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
• Multi-orientation macros of 4, 8 and 16 lane SERDES are available for most common metal stacks
• Exhibits exceptional input sensitivity, input jitter tolerance and low output jitter
• Enterprise class Long Reach 8-tap DFE supporting beyond standard PCIe Channels
• Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and DFE
• Finely configurable driver impedance, amplitude and 3-tap FFE
• Supports multiple low-power modes
• Test support features such as ac-JTAG, near-end loopback, reverse loopback, PRBS generator+checker, PLL bypass modes, etc.
• Includes PIPE Compliant PCIe PCS with programmable PIPE frequencies, and supporting bifurcation, lane/link powerdown, SRNS, SRIS and L1-substates
• Supports industry standard third-party controllers for PCIe
• Low pin-count and suitable for a variety of flip-chip packages when paired with onchip T-coils
• Metallization scheme and pad/bump structures customizable to specifications