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Vendor:
CAST
Category:
GPIO
General-Purpose I/O Controller Core
The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple inp…
Overview
The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output software-controlled signals.
The number of general-purpose I/O signals is user selectable ranging from 1 to 32. For more I/O signals, several GPIO cores can be used in parallel. Each GPIO signal can be programmed individually as an input, an input in interrupt mode, an output, a bi-directional I/O, or as driven by an auxiliary input. GPIO signals programmed as inputs can be registered at the rising edge of the system clock or at a user-programmed edge of the external clock.
The GPIO core is rigorously verified, silicon-proven and available in RTL source or as a targeted FPGA netlist.
The number of general-purpose I/O signals is user selectable ranging from 1 to 32. For more I/O signals, several GPIO cores can be used in parallel. Each GPIO signal can be programmed individually as an input, an input in interrupt mode, an output, a bi-directional I/O, or as driven by an auxiliary input. GPIO signals programmed as inputs can be registered at the rising edge of the system clock or at a user-programmed edge of the external clock.
The GPIO core is rigorously verified, silicon-proven and available in RTL source or as a targeted FPGA netlist.
Key features
- User selectable number of GPIO signals from 1 to 32
- All GPIO signals can be bi-directional (external bi-directional I/O cells are required in that case)
- All GPIO signals can be tri-stated or open-drain enabled (external tri-state or open-drain I/O cells are required in that case)
- GPIO signals programmed as in-puts can cause an interrupt request to the CPU
- All GPIO signals are programmed as inputs at hardware reset
- Auxiliary inputs to the GPIO core bypass outputs from RGPIO_OUT register
- Alternative input reference clock signal from external interface
- 32-bit AHB interface (contact CAST for other interfaces)
- Extremely configurable (implementation of registers, external clock inverted versus negative edge flip-flops etc.)
Block Diagram
GPIO block diagram
Applications
- The GPIO core can be used in a wide range of applications where simple I/O control is needed.
What’s Included?
- Synthesizable RTL or FPGA netlist
- Testbench & sample test cases
- Simulation & synthesis scripts
- Documentation
Specifications
Identity
Part Number
GPIO
Vendor
CAST
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about GPIO IP cores
What is General-Purpose I/O Controller Core?
General-Purpose I/O Controller Core is a GPIO IP core from CAST listed on Semi IP Hub.
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.